diff options
author | Stefan Agner <stefan@agner.ch> | 2016-05-02 19:13:19 -0700 |
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committer | Stefan Agner <stefan@agner.ch> | 2016-05-09 17:17:05 -0700 |
commit | 21d6d84123de8e6e2ebdf5543b530403951b3059 (patch) | |
tree | 046a7fa39e1c7cff49792ac67f1ae899271a56b7 /examples/imx7_colibri_m4/board.c | |
parent | 2fb8ccd4adf6433033a402e2fa07c2f11c489518 (diff) |
resync with FreeRTOS_BSP_1.0.1_iMX7D
Diffstat (limited to 'examples/imx7_colibri_m4/board.c')
-rw-r--r-- | examples/imx7_colibri_m4/board.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/examples/imx7_colibri_m4/board.c b/examples/imx7_colibri_m4/board.c index 37ea77b..4c48c00 100644 --- a/examples/imx7_colibri_m4/board.c +++ b/examples/imx7_colibri_m4/board.c @@ -42,13 +42,19 @@ void BOARD_ClockInit(void) { /* OSC/PLL is already initialized by Cortex-A7 (u-boot) */ - /* Disable WDOG3 */ + /* + * Disable WDOG3 + * Note : The WDOG clock Root is shared by all the 4 WDOGs, so FreeROTS + * code should avoid closing it + */ CCM_UpdateRoot(CCM, ccmRootWdog, ccmRootmuxWdogOsc24m, 0, 0); CCM_EnableRoot(CCM, ccmRootWdog); CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNeededRun); + + RDC_SetPdapAccess(RDC, BOARD_WDOG_RDC_PDAP, 3 << (BOARD_DOMAIN_ID * 2), false, false); WDOG_DisablePowerdown(BOARD_WDOG_BASEADDR); + CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNotNeeded); - CCM_DisableRoot(CCM, ccmRootWdog); /* We need system PLL Div2 to run M4 core */ CCM_ControlGate(CCM, ccmPllGateSys, ccmClockNeededRun); @@ -75,7 +81,12 @@ void dbg_uart_init(void) CCM_UpdateRoot(CCM, BOARD_DEBUG_UART_CCM_ROOT, ccmRootmuxUartOsc24m, 0, 0); /* Enable debug uart clock */ CCM_EnableRoot(CCM, BOARD_DEBUG_UART_CCM_ROOT); - CCM_ControlGate(CCM, BOARD_DEBUG_UART_CCM_CCGR, ccmClockNeededRunWait); + /* + * IC Limitation + * M4 stop will cause A7 UART lose functionality + * So we need UART clock all the time + */ + CCM_ControlGate(CCM, BOARD_DEBUG_UART_CCM_CCGR, ccmClockNeededAll); /* Config debug uart pins */ configure_uart_pins(BOARD_DEBUG_UART_BASEADDR); |