summaryrefslogtreecommitdiff
path: root/board
diff options
context:
space:
mode:
authorDominik Sliwa <dominik.sliwa@toradex.com>2018-09-11 15:35:14 +0200
committerDominik Sliwa <dominik.sliwa@toradex.com>2018-09-11 15:35:14 +0200
commitf3f54d37d7888235bccac1c0cddda1dd9b2323f4 (patch)
treebd68068e0b7889a09779973e0e494f5d73acd2ac /board
parent4d7f3aebc85ff3928a25bd1567f94f2789d6437b (diff)
implement SWO debugging
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Diffstat (limited to 'board')
-rw-r--r--board/board.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/board/board.c b/board/board.c
index 726870b..ba853ad 100644
--- a/board/board.c
+++ b/board/board.c
@@ -38,8 +38,23 @@
* @brief initialize debug console to enable printf for this demo/example
*/
void BOARD_InitDebugConsole(void) {
- uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
- DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+#ifdef USE_SWO
+ uint32_t SWOSpeed = 1000000; /* default 64k baud rate */
+ uint32_t SWOPrescaler = (uartClkSrcFreq / SWOSpeed) - 1; /* SWOSpeed in Hz, note that cpuCoreFreqHz is expected to be match the CPU core clock */
+ CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; /* enable trace in core debug */
+ *((volatile unsigned *)(ITM_BASE + 0x400F0)) = 0x00000002; /* "Selected PIN Protocol Register": Select which protocol to use for trace output (2: SWO NRZ, 1: SWO Manchester encoding) */
+ *((volatile unsigned *)(ITM_BASE + 0x40010)) = SWOPrescaler; /* "Async Clock Prescaler Register". Scale the baud rate of the asynchronous output */
+ *((volatile unsigned *)(ITM_BASE + 0x00FB0)) = 0xC5ACCE55; /* ITM Lock Access Register, C5ACCE55 enables more write access to Control Register 0xE00 :: 0xFFC */
+ ITM->TCR = ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_ITMENA_Msk; /* ITM Trace Control Register */
+ ITM->TPR = ITM_TPR_PRIVMASK_Msk; /* ITM Trace Privilege Register */
+ ITM->TER = 0x01; /* ITM Trace Enable Register. Enabled tracing on stimulus ports. One bit per stimulus port. */
+ *((volatile unsigned *)(ITM_BASE + 0x01000)) = 0x400003FE; /* DWT_CTRL */
+ *((volatile unsigned *)(ITM_BASE + 0x40304)) = 0x00000100; /* Formatter and Flush Control Register */
+
+#endif
+
+DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
}