diff options
| author | Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> | 2016-10-03 21:00:10 +0530 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2016-10-03 18:20:30 -0700 |
| commit | 919c42c5646a775bb432c210c32b27df577250f2 (patch) | |
| tree | 041ee588e730af869528e6c99093ea4e0fce3956 | |
| parent | 0832c202066a2fae355fe4f9ea08500a49d97f05 (diff) | |
platform: devices: VF6XX: Add missing reserved address loactions for IOMUX registers
Add missing reserved addr loacations to avoid getting wrong offset address.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | platform/devices/VF6XX/include/VF6XX_M4.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/platform/devices/VF6XX/include/VF6XX_M4.h b/platform/devices/VF6XX/include/VF6XX_M4.h index b191ef1..c0e8bad 100644 --- a/platform/devices/VF6XX/include/VF6XX_M4.h +++ b/platform/devices/VF6XX/include/VF6XX_M4.h @@ -1105,6 +1105,7 @@ typedef struct { __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE27; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE28; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA7; + __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_RESETB; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A15; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A14; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A13; @@ -1154,6 +1155,7 @@ typedef struct { __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_ODT1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DDRBYTE1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DDRBYTE2; + __IO uint32_t RESERVED_0[2]; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT; @@ -1340,6 +1342,7 @@ typedef struct { #define IOMUXC_SW_MUX_CTL_PAD_PTE27_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE27) #define IOMUXC_SW_MUX_CTL_PAD_PTE28_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE28) #define IOMUXC_SW_MUX_CTL_PAD_PTA7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA7) +#define IOMUXC_SW_MUX_CTL_PAD_DDR_RESETB_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_RESETB) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A15_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A15) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A14_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A14) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A13_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A13) @@ -1583,6 +1586,7 @@ typedef struct { #define IOMUXC_PTE27 IOMUXC_SW_MUX_CTL_PAD_PTE27_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE28 IOMUXC_SW_MUX_CTL_PAD_PTE28_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA7 IOMUXC_SW_MUX_CTL_PAD_PTA7_REG(IOMUXC_BASE_PTR) +#define IOMUXC_DDR_RESETB IOMUXC_SW_MUX_CTL_PAD_DDR_RESETB_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A15 IOMUXC_SW_MUX_CTL_PAD_DDR_A15_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A14 IOMUXC_SW_MUX_CTL_PAD_DDR_A14_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A13 IOMUXC_SW_MUX_CTL_PAD_DDR_A13_REG(IOMUXC_BASE_PTR) |