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authorStefan Agner <stefan.agner@toradex.com>2016-11-10 11:04:39 -0800
committerStefan Agner <stefan.agner@toradex.com>2016-11-10 11:13:38 -0800
commit1dd1ebb712a8e0af2d140edf88363ecb73050d25 (patch)
tree48db0c0f607a26c35de875b1ada50eb363180c8f
parentcd6c66301a83dde9ad4eaf675459a0348f4732cf (diff)
adjust DDR locations to be at the end of 256MiB boundary
The linker file to build a firmware running from DDR memory (MCIMX7D_M4_ddr.ld) currently puts the firmware at the end of the 512MiB boundary. That is not a valid memory area for the Colibri iMX7S module (which comes with 256MiB of DDR memory). In practise it actually does work because out-of-bound addresses usually just mirror the content of the lower address, but it is a behavior which should not be relied upon. This change moves the firmware location to a valid location for all our modules at the end of the 256MiB boundary (0x8ff00000, allows for a firmware up to ~960kiB). Furthermore, the VirtIO VRING offset is currently at the end of the 1024MiB boundary. Again, due to the mirroring behavior this worked in practise, but it should not be relied upon. Hence move the VRING to the end of the 256MiB boundary too (0x8fff0000). The firmware size has been choosen so that the VRING just fits after the firmware. Note that since the VRING offsets are hardcoded, this change needs a corresponding change in the Linux kernel source: arch/arm/mach-imx/imx_rpmsg.c (function imx_rpmsg_probe) Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
-rw-r--r--middleware/multicore/open-amp/porting/imx7d_m4/platform_info.c4
-rw-r--r--platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld4
2 files changed, 4 insertions, 4 deletions
diff --git a/middleware/multicore/open-amp/porting/imx7d_m4/platform_info.c b/middleware/multicore/open-amp/porting/imx7d_m4/platform_info.c
index 4aa2c4a..c7f6f3c 100644
--- a/middleware/multicore/open-amp/porting/imx7d_m4/platform_info.c
+++ b/middleware/multicore/open-amp/porting/imx7d_m4/platform_info.c
@@ -54,8 +54,8 @@ extern struct hil_platform_ops proc_ops;
/*
* Linux has a different alignment requirement, and its have 512 buffers instead of 32 buffers for the 2 ring
*/
-#define VRING0_BASE 0xBFFF0000
-#define VRING1_BASE 0xBFFF8000
+#define VRING0_BASE 0x8FFF0000
+#define VRING1_BASE 0x8FFF8000
/* IPI_VECT here defines VRING index in MU */
#define VRING0_IPI_VECT 0
diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld
index 84c0301..92f1d6e 100644
--- a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld
+++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld
@@ -55,8 +55,8 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Specify the memory areas */
MEMORY
{
- m_interrupts (RX) : ORIGIN = 0x9ff00000, LENGTH = 0x00000240
- m_text (RX) : ORIGIN = 0x9ff00240, LENGTH = 0x00007DC0
+ m_interrupts (RX) : ORIGIN = 0x8ff00000, LENGTH = 0x00000240
+ m_text (RX) : ORIGIN = 0x8ff00240, LENGTH = 0x000EFDC0
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}