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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-06-20 02:42:03 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-08-27 02:28:34 +0200
commit9588d2f52965826d60e839828ab8408903c75549 (patch)
tree35fa24d79a32ea820b9631358d1213a4a0ab071b
parentf4ae60f83d50473851e24c76e1c40bbecf877320 (diff)
overlays: verdin-imx8mm_sn65dsi84_overlay: verdin dsi to lvds adapter
Add device tree overlay for Verdin DSI to LVDS Adapter orderable at Toradex. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--overlays/verdin-imx8mm_sn65dsi84_overlay.dts124
1 files changed, 124 insertions, 0 deletions
diff --git a/overlays/verdin-imx8mm_sn65dsi84_overlay.dts b/overlays/verdin-imx8mm_sn65dsi84_overlay.dts
new file mode 100644
index 0000000..4c0d618
--- /dev/null
+++ b/overlays/verdin-imx8mm_sn65dsi84_overlay.dts
@@ -0,0 +1,124 @@
+// Verdin DSI to LVDS Adapter orderable at Toradex.
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "dt-bindings/pwm/pwm.h"
+
+/ {
+ compatible = "toradex,verdin-imx8mm";
+
+ backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 45 63 88 119 158 203 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dsi_bkl_en>;
+ power-supply = <&reg_3p3v>;
+ pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
+ };
+};
+
+&{/soc@0/bus@32c00000/display-subsystem} {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&pwm1 {
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_1>;
+ status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&i2c2 {
+ clock-frequency = <10000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&i2c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ bridge@2c {
+ compatible = "ti,sn65dsi83";
+ enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>;
+ reg = <0x2c>;
+ ti,dsi-lanes = <4>;
+ ti,height-mm = <136>;
+ ti,lvds-bpp = <24>;
+ ti,lvds-format = <2>;
+ ti,width-mm = <217>;
+
+ display-timings {
+ native-mode = <&lvds_timing0>;
+
+ lvds_timing0: lt170410_2whc {
+ /*
+ * Take the minimum pixelclock as 71.1 MHz is
+ * not working on NXP i.MX8M Mini
+ */
+ clock-frequency = <68900000>;
+ hactive = <1280 1280 1280>;
+ hfront-porch = <23 60 71>;
+ hback-porch = <23 60 71>;
+ hsync-len = <15 40 47>;
+ vactive = <800 800 800>;
+ vfront-porch = <5 7 10>;
+ vback-porch = <5 7 10>;
+ vsync-len = <6 9 12>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+
+ port {
+ dsi85_in: endpoint {
+ remote-endpoint = <&mipi_dsi_bridge1_out>;
+ };
+ };
+ };
+
+ touch@4a {
+ compatible = "atmel,maxtouch";
+ interrupt-parent = <&gpio3>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 17 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_hpd>, <&pinctrl_gpio2>;
+ reg = <0x4a>;
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* SODIMM 208 */
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&mipi_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_bridge1_out: endpoint {
+ remote-endpoint = <&dsi85_in>;
+ attach-bridge;
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+};