diff options
author | Dominik Sliwa <dominik.sliwa@toradex.com> | 2019-03-04 12:01:54 +0100 |
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committer | Dominik Sliwa <dominik.sliwa@toradex.com> | 2019-03-04 12:01:54 +0100 |
commit | 348fa3f6871f56a37dcd16c99ca98118c6d79a38 (patch) | |
tree | 6fcae7785bae4ffb838fd6549f7d01ba6abf0763 /drivers/staging/rtl8723bs/include/hal_phy_cfg.h |
Backports v4.19.24
Backports generated by toradex backports 515a1fa55cda2b1d952872e1786857481bd54fcc
against mainline kernel tag v4.19.24
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Diffstat (limited to 'drivers/staging/rtl8723bs/include/hal_phy_cfg.h')
-rw-r--r-- | drivers/staging/rtl8723bs/include/hal_phy_cfg.h | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/drivers/staging/rtl8723bs/include/hal_phy_cfg.h b/drivers/staging/rtl8723bs/include/hal_phy_cfg.h new file mode 100644 index 0000000..640427f --- /dev/null +++ b/drivers/staging/rtl8723bs/include/hal_phy_cfg.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __INC_HAL8723BPHYCFG_H__ +#define __INC_HAL8723BPHYCFG_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOOP_LIMIT 5 +#define MAX_STALL_TIME 50 /* us */ +#define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */ +#define MAX_TXPWR_IDX_NMODE_92S 63 +#define Reset_Cnt_Limit 3 + +#define MAX_AGGR_NUM 0x07 + + +/*--------------------------Define Parameters End-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure End----------------------------*/ + +/*--------------------------Exported Function prototype---------------------*/ +u32 +PHY_QueryBBReg_8723B( +struct adapter *Adapter, +u32 RegAddr, +u32 BitMask + ); + +void +PHY_SetBBReg_8723B( +struct adapter *Adapter, +u32 RegAddr, +u32 BitMask, +u32 Data + ); + +u32 +PHY_QueryRFReg_8723B( +struct adapter * Adapter, +u8 eRFPath, +u32 RegAddr, +u32 BitMask + ); + +void +PHY_SetRFReg_8723B( +struct adapter * Adapter, +u8 eRFPath, +u32 RegAddr, +u32 BitMask, +u32 Data + ); + +/* MAC/BB/RF HAL config */ +int PHY_BBConfig8723B(struct adapter *Adapter ); + +int PHY_RFConfig8723B(struct adapter *Adapter ); + +s32 PHY_MACConfig8723B(struct adapter *padapter); + +void +PHY_SetTxPowerIndex_8723B( +struct adapter * Adapter, +u32 PowerIndex, +u8 RFPath, +u8 Rate + ); + +u8 +PHY_GetTxPowerIndex_8723B( +struct adapter * padapter, +u8 RFPath, +u8 Rate, +enum CHANNEL_WIDTH BandWidth, +u8 Channel + ); + +void +PHY_GetTxPowerLevel8723B( +struct adapter * Adapter, + s32* powerlevel + ); + +void +PHY_SetTxPowerLevel8723B( +struct adapter * Adapter, +u8 channel + ); + +void +PHY_SetBWMode8723B( +struct adapter * Adapter, +enum CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ +unsigned char Offset /* Upper, Lower, or Don't care */ +); + +void +PHY_SwChnl8723B(/* Call after initialization */ +struct adapter *Adapter, +u8 channel + ); + +void +PHY_SetSwChnlBWMode8723B( +struct adapter * Adapter, +u8 channel, +enum CHANNEL_WIDTH Bandwidth, +u8 Offset40, +u8 Offset80 +); + +/*--------------------------Exported Function prototype End---------------------*/ + +#endif |