diff options
| author | Dominik Sliwa <dominik.sliwa@toradex.com> | 2019-03-04 12:01:54 +0100 |
|---|---|---|
| committer | Dominik Sliwa <dominik.sliwa@toradex.com> | 2019-03-04 12:01:54 +0100 |
| commit | 348fa3f6871f56a37dcd16c99ca98118c6d79a38 (patch) | |
| tree | 6fcae7785bae4ffb838fd6549f7d01ba6abf0763 /drivers/staging/rtl8188eu/include | |
Backports v4.19.24
Backports generated by toradex backports 515a1fa55cda2b1d952872e1786857481bd54fcc
against mainline kernel tag v4.19.24
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Diffstat (limited to 'drivers/staging/rtl8188eu/include')
58 files changed, 12211 insertions, 0 deletions
diff --git a/drivers/staging/rtl8188eu/include/HalVerDef.h b/drivers/staging/rtl8188eu/include/HalVerDef.h new file mode 100644 index 0000000..63a144e --- /dev/null +++ b/drivers/staging/rtl8188eu/include/HalVerDef.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __HAL_VERSION_DEF_H__ +#define __HAL_VERSION_DEF_H__ + +enum HAL_CHIP_TYPE { + TEST_CHIP = 0, + NORMAL_CHIP = 1, + FPGA = 2, +}; + +enum HAL_CUT_VERSION { + A_CUT_VERSION = 0, + B_CUT_VERSION = 1, + C_CUT_VERSION = 2, + D_CUT_VERSION = 3, + E_CUT_VERSION = 4, + F_CUT_VERSION = 5, + G_CUT_VERSION = 6, +}; + +enum HAL_VENDOR { + CHIP_VENDOR_TSMC = 0, + CHIP_VENDOR_UMC = 1, +}; + +struct HAL_VERSION { + enum HAL_CHIP_TYPE ChipType; + enum HAL_CUT_VERSION CUTVersion; + enum HAL_VENDOR VendorType; +}; + +#endif diff --git a/drivers/staging/rtl8188eu/include/basic_types.h b/drivers/staging/rtl8188eu/include/basic_types.h new file mode 100644 index 0000000..b69b45d --- /dev/null +++ b/drivers/staging/rtl8188eu/include/basic_types.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __BASIC_TYPES_H__ +#define __BASIC_TYPES_H__ + +#include <linux/types.h> +#define NDIS_OID uint + +/* port from fw */ +/* TODO: Macros Below are Sync from SD7-Driver. It is necessary + * to check correctness + */ + +/* + * Call endian free function when + * 1. Read/write packet content. + * 2. Before write integer to IO. + * 3. After read integer from IO. + */ + +/* Convert little data endian to host ordering */ +#define EF1BYTE(_val) \ + ((u8)(_val)) +#define EF2BYTE(_val) \ + (le16_to_cpu(_val)) +#define EF4BYTE(_val) \ + (le32_to_cpu(_val)) + +/* Create a bit mask + * Examples: + * BIT_LEN_MASK_32(0) => 0x00000000 + * BIT_LEN_MASK_32(1) => 0x00000001 + * BIT_LEN_MASK_32(2) => 0x00000003 + * BIT_LEN_MASK_32(32) => 0xFFFFFFFF + */ +#define BIT_LEN_MASK_32(__bitlen) \ + (0xFFFFFFFF >> (32 - (__bitlen))) +#define BIT_LEN_MASK_16(__bitlen) \ + (0xFFFF >> (16 - (__bitlen))) +#define BIT_LEN_MASK_8(__bitlen) \ + (0xFF >> (8 - (__bitlen))) + +/* Create an offset bit mask + * Examples: + * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 + * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 + */ +#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ + (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) +#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ + (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) +#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ + (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) + +/*Description: + * Return 4-byte value in host byte ordering from + * 4-byte pointer in little-endian system. + */ +#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ + (EF4BYTE(*((__le32 *)(__pstart)))) +#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ + (EF2BYTE(*((__le16 *)(__pstart)))) +#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ + (EF1BYTE(*((u8 *)(__pstart)))) + +/* Description: + * Translate subfield (continuous bits in little-endian) of 4-byte + * value to host byte ordering. + */ +#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ + ( \ + (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ + BIT_LEN_MASK_32(__bitlen) \ + ) +#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ + ( \ + (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ + BIT_LEN_MASK_16(__bitlen) \ + ) +#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ + ( \ + (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ + BIT_LEN_MASK_8(__bitlen) \ + ) + +/* Description: + * Mask subfield (continuous bits in little-endian) of 4-byte value + * and return the result in 4-byte value in host byte ordering. + */ +#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ + ( \ + LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ + (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ + ) +#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ + ( \ + LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ + (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ + ) +#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ + ( \ + LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ + (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ + ) + +/* Description: + * Set subfield of little-endian 4-byte value to specified value. + */ +#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ + *((u32 *)(__pstart)) = \ + ( \ + LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ + ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ + ) + +#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ + *((u16 *)(__pstart)) = \ + ( \ + LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ + ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ + ); + +#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ + *((u8 *)(__pstart)) = EF1BYTE \ + ( \ + LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ + ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ + ) + +#endif /* __BASIC_TYPES_H__ */ diff --git a/drivers/staging/rtl8188eu/include/drv_types.h b/drivers/staging/rtl8188eu/include/drv_types.h new file mode 100644 index 0000000..4ae0958 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/drv_types.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +/*----------------------------------------------------------------------------- + + For type defines and data structure defines + +------------------------------------------------------------------------------*/ + + +#ifndef __DRV_TYPES_H__ +#define __DRV_TYPES_H__ + +#define DRV_NAME "r8188eu" + +#include <osdep_service.h> +#include <wlan_bssdef.h> +#include <rtw_ht.h> +#include <rtw_cmd.h> +#include <rtw_xmit.h> +#include <rtw_recv.h> +#include <hal_intf.h> +#include <hal_com.h> +#include <rtw_qos.h> +#include <rtw_security.h> +#include <rtw_pwrctrl.h> +#include <rtw_eeprom.h> +#include <sta_info.h> +#include <rtw_mlme.h> +#include <rtw_debug.h> +#include <rtw_rf.h> +#include <rtw_event.h> +#include <rtw_led.h> +#include <rtw_mlme_ext.h> +#include <rtw_ap.h> + +#define SPEC_DEV_ID_NONE BIT(0) +#define SPEC_DEV_ID_DISABLE_HT BIT(1) +#define SPEC_DEV_ID_ENABLE_PS BIT(2) +#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) +#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) +#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) + +struct registry_priv { + struct ndis_802_11_ssid ssid; + u8 channel;/* ad-hoc support requirement */ + u8 wireless_mode;/* A, B, G, auto */ + u8 preamble;/* long, short, auto */ + u8 vrtl_carrier_sense;/* Enable, Disable, Auto */ + u8 vcs_type;/* RTS/CTS, CTS-to-self */ + u16 rts_thresh; + u16 frag_thresh; + u8 power_mgnt; + u8 ips_mode; + u8 smart_ps; + u8 mp_mode; + u8 acm_method; + /* UAPSD */ + u8 wmm_enable; + u8 uapsd_enable; + + struct wlan_bssid_ex dev_network; + + u8 ht_enable; + u8 cbw40_enable; + u8 ampdu_enable;/* for tx */ + u8 rx_stbc; + u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */ + + u8 wifi_spec;/* !turbo_mode */ + + u8 channel_plan; + bool accept_addba_req; /* true = accept AP's Add BA req */ + + u8 antdiv_cfg; + u8 antdiv_type; + + u8 usbss_enable;/* 0:disable,1:enable */ + u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */ + + u8 max_roaming_times; /* the max number driver will try */ + + u8 fw_iol; /* enable iol without other concern */ + + u8 enable80211d; + + u8 ifname[16]; + u8 if2name[16]; + + u8 notch_filter; + bool monitor_enable; +}; + +#define MAX_CONTINUAL_URB_ERR 4 + +struct dvobj_priv { + struct adapter *if1; + /* For 92D, DMDP have 2 interface. */ + u8 InterfaceNumber; + u8 NumInterfaces; + + /* In /Out Pipe information */ + int RtInPipe[2]; + int RtOutPipe[3]; + u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */ + +/*-------- below is for USB INTERFACE --------*/ + u8 ishighspeed; + u8 RtNumInPipes; + u8 RtNumOutPipes; + struct mutex usb_vendor_req_mutex; + + struct usb_interface *pusbintf; + struct usb_device *pusbdev; +}; + +static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj) +{ + /* todo: get interface type from dvobj and the return + * the dev accordingly + */ + return &dvobj->pusbintf->dev; +}; + +struct adapter { + struct dvobj_priv *dvobj; + struct mlme_priv mlmepriv; + struct mlme_ext_priv mlmeextpriv; + struct cmd_priv cmdpriv; + struct xmit_priv xmitpriv; + struct recv_priv recvpriv; + struct sta_priv stapriv; + struct security_priv securitypriv; + struct registry_priv registrypriv; + struct pwrctrl_priv pwrctrlpriv; + struct eeprom_priv eeprompriv; + struct led_priv ledpriv; + + struct hal_data_8188e *HalData; + + s32 bDriverStopped; + s32 bSurpriseRemoved; + + u8 hw_init_completed; + + void *cmdThread; + struct net_device *pnetdev; + struct net_device *pmondev; + + int bup; + struct net_device_stats stats; + struct iw_statistics iwstats; + struct proc_dir_entry *dir_dev;/* for proc directory */ + + int net_closed; + u8 bFWReady; + u8 bReadPortCancel; + u8 bWritePortCancel; + + struct mutex hw_init_mutex; +}; + +#define adapter_to_dvobj(adapter) (adapter->dvobj) + +static inline u8 *myid(struct eeprom_priv *peepriv) +{ + return peepriv->mac_addr; +} + +#endif /* __DRV_TYPES_H__ */ diff --git a/drivers/staging/rtl8188eu/include/fw.h b/drivers/staging/rtl8188eu/include/fw.h new file mode 100644 index 0000000..9f010c4 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/fw.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2009-2013 Realtek Corporation. + * + * Contact Information: + * wlanfae <wlanfae@realtek.com> + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * Larry Finger <Larry.Finger@lwfinger.net> + * + *****************************************************************************/ +#include "drv_types.h" +#include <linux/types.h> + +#ifndef __RTL92C__FW__H__ +#define __RTL92C__FW__H__ + +#define FW_8192C_START_ADDRESS 0x1000 +#define FW_8192C_PAGE_SIZE 4096 +#define FW_8192C_POLLING_DELAY 5 + +struct rtl92c_firmware_header { + __le16 signature; + u8 category; + u8 function; + u16 version; + u8 subversion; + u8 rsvd1; + u8 month; + u8 date; + u8 hour; + u8 minute; + u16 ramcodesize; + u16 rsvd2; + u32 svnindex; + u32 rsvd3; + u32 rsvd4; + u32 rsvd5; +}; + +int rtl88eu_download_fw(struct adapter *adapt); + +#endif diff --git a/drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h b/drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h new file mode 100644 index 0000000..da66695 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __INC_HAL8188EPHYCFG_H__ +#define __INC_HAL8188EPHYCFG_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +#define LOOP_LIMIT 5 +#define MAX_STALL_TIME 50 /* us */ +#define AntennaDiversityValue 0x80 +#define MAX_TXPWR_IDX_NMODE_92S 63 +#define Reset_Cnt_Limit 3 + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM 9 +#define HP_THERMAL_NUM 8 + +#define MAX_AGGR_NUM 0x07 + + +/*--------------------------Define Parameters-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ +enum sw_chnl_cmd_id { + CmdID_End, + CmdID_SetTxPowerLevel, + CmdID_BBRegWrite10, + CmdID_WritePortUlong, + CmdID_WritePortUshort, + CmdID_WritePortUchar, + CmdID_RF_WriteReg, +}; + +/* 1. Switch channel related */ +struct sw_chnl_cmd { + enum sw_chnl_cmd_id CmdID; + u32 Para1; + u32 Para2; + u32 msDelay; +}; + +enum hw90_block { + HW90_BLOCK_MAC = 0, + HW90_BLOCK_PHY0 = 1, + HW90_BLOCK_PHY1 = 2, + HW90_BLOCK_RF = 3, + HW90_BLOCK_MAXIMUM = 4, /* Never use this */ +}; + +enum rf_radio_path { + RF_PATH_A = 0, /* Radio Path A */ + RF_PATH_B = 1, /* Radio Path B */ +}; + +#define MAX_PG_GROUP 13 + +#define RF_PATH_MAX 2 +#define MAX_RF_PATH RF_PATH_MAX +#define MAX_TX_COUNT 4 /* path numbers */ + +#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */ +#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8, + *ch9~11, ch12~13, CH 14 + * total three groups + */ +#define CHANNEL_GROUP_MAX_88E 6 + +enum wireless_mode { + WIRELESS_MODE_UNKNOWN = 0x00, + WIRELESS_MODE_A = BIT(2), + WIRELESS_MODE_B = BIT(0), + WIRELESS_MODE_G = BIT(1), + WIRELESS_MODE_AUTO = BIT(5), + WIRELESS_MODE_N_24G = BIT(3), + WIRELESS_MODE_N_5G = BIT(4), + WIRELESS_MODE_AC = BIT(6) +}; + +enum phy_rate_tx_offset_area { + RA_OFFSET_LEGACY_OFDM1, + RA_OFFSET_LEGACY_OFDM2, + RA_OFFSET_HT_OFDM1, + RA_OFFSET_HT_OFDM2, + RA_OFFSET_HT_OFDM3, + RA_OFFSET_HT_OFDM4, + RA_OFFSET_HT_CCK, +}; + +struct bb_reg_def { + u32 rfintfs; /* set software control: */ + /* 0x870~0x877[8 bytes] */ + u32 rfintfi; /* readback data: */ + /* 0x8e0~0x8e7[8 bytes] */ + u32 rfintfo; /* output data: */ + /* 0x860~0x86f [16 bytes] */ + u32 rfintfe; /* output enable: */ + /* 0x860~0x86f [16 bytes] */ + u32 rf3wireOffset; /* LSSI data: */ + /* 0x840~0x84f [16 bytes] */ + u32 rfLSSI_Select; /* BB Band Select: */ + /* 0x878~0x87f [8 bytes] */ + u32 rfTxGainStage; /* Tx gain stage: */ + /* 0x80c~0x80f [4 bytes] */ + u32 rfHSSIPara1; /* wire parameter control1 : */ + /* 0x820~0x823,0x828~0x82b, + * 0x830~0x833, 0x838~0x83b [16 bytes] + */ + u32 rfHSSIPara2; /* wire parameter control2 : */ + /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, + * 0x83c~0x83f [16 bytes] + */ + u32 rfSwitchControl; /* Tx Rx antenna control : */ + /* 0x858~0x85f [16 bytes] */ + u32 rfAGCControl1; /* AGC parameter control1 : */ + /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, + * 0xc68~0xc6b [16 bytes] + */ + u32 rfAGCControl2; /* AGC parameter control2 : */ + /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, + * 0xc6c~0xc6f [16 bytes] + */ + u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */ + /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, + * 0xc2c~0xc2f [16 bytes] + */ + u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, + * Rx DC notch filter : + */ + /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, + * 0xc28~0xc2b [16 bytes] + */ + u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */ + /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, + * 0xc98~0xc9b [16 bytes] + */ + u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */ + /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, + * 0xc9c~0xc9f [16 bytes] + */ + u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ + /* 0x8a0~0x8af [16 bytes] */ + u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for + * Path A and B + */ +}; + +/*------------------------------Define structure----------------------------*/ + + +/*------------------------Export global variable----------------------------*/ +/*------------------------Export global variable----------------------------*/ + + +/*------------------------Export Marco Definition---------------------------*/ +/*------------------------Export Marco Definition---------------------------*/ + + +/*--------------------------Exported Function prototype---------------------*/ +/* */ +/* BB and RF register read/write */ +/* */ + +/* Read initi reg value for tx power setting. */ +void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter); + +/* BB TX Power R/W */ +void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel); + +void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation); + +/* Call after initialization */ +void ChkFwCmdIoDone(struct adapter *adapter); + +/* BB/MAC/RF other monitor API */ +void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main); + +void PHY_SwitchEphyParameter(struct adapter *adapter); + +void PHY_EnableHostClkReq(struct adapter *adapter); + +bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant); + +/*--------------------------Exported Function prototype---------------------*/ + +#define PHY_SetMacReg PHY_SetBBReg + +#define SIC_HW_SUPPORT 0 + +#define SIC_MAX_POLL_CNT 5 + +#define SIC_CMD_READY 0 +#define SIC_CMD_WRITE 1 +#define SIC_CMD_READ 2 + +#define SIC_CMD_REG 0x1EB /* 1byte */ +#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */ +#define SIC_DATA_REG 0x1EC /* 1bc~1bf */ + +#endif /* __INC_HAL8192CPHYCFG_H */ diff --git a/drivers/staging/rtl8188eu/include/hal8188e_phy_reg.h b/drivers/staging/rtl8188eu/include/hal8188e_phy_reg.h new file mode 100644 index 0000000..53afcea --- /dev/null +++ b/drivers/staging/rtl8188eu/include/hal8188e_phy_reg.h @@ -0,0 +1,1082 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __INC_HAL8188EPHYREG_H__ +#define __INC_HAL8188EPHYREG_H__ +/*--------------------------Define Parameters-------------------------------*/ +/* */ +/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ +/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ +/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ +/* 3. RF register 0x00-2E */ +/* 4. Bit Mask for BB/RF register */ +/* 5. Other definition for BB/RF R/W */ +/* */ + + +/* */ +/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ +/* 1. Page1(0x100) */ +/* */ +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +/* 2. Page2(0x200) */ +/* The following two definition are only used for USB interface. */ +#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB r/w cmd address. */ +#define RF_BB_CMD_DATA 0x02c4 /* RF/BB r/w cmd data. */ + +/* 3. Page8(0x800) */ +#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ + +#define rFPGA0_TxInfo 0x804 /* Status report?? */ +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ + +#define rFPGA0_RFTiming1 0x810 /* Useless now */ +#define rFPGA0_RFTiming2 0x814 + +#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c + +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 + +#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ +#define rFPGA0_XB_RFInterfaceOE 0x864 + +#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */ +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ +#define rFPGA0_XCD_RFParameter 0x87c + +/* Crystal cap setting RF-R/W protection for parameter4?? */ +#define rFPGA0_AnalogParameter1 0x880 +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 +/* enable ad/da clock1 for dual-phy */ +#define rFPGA0_AdDaClockEn 0x888 +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 /* Useless now */ +/* Transceiver A HSPI Readback */ +#define TransceiverA_HSPI_Readback 0x8b8 +/* Transceiver B HSPI Readback */ +#define TransceiverB_HSPI_Readback 0x8bc +/* Useless now RF Interface Readback Value */ +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ + +/* 4. Page9(0x900) */ +/* RF mode & OFDM TxSC RF BW Setting?? */ +#define rFPGA1_RFMOD 0x900 + +#define rFPGA1_TxBlock 0x904 /* Useless now */ +#define rFPGA1_DebugSelect 0x908 /* Useless now */ +#define rFPGA1_TxInfo 0x90c /* Useless now Status report */ + +/* 5. PageA(0xA00) */ +/* Set Control channel to upper or lower - required only for 40MHz */ +#define rCCK0_System 0xa00 + +/* Disable init gain now Select RX path by RSSI */ +#define rCCK0_AFESetting 0xa04 +/* Disable init gain now Init gain */ +#define rCCK0_CCA 0xa08 + +/* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, + * RX LNA Threshold useless now. Not the same as 90 series + */ +#define rCCK0_RxAGC1 0xa0c +#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ + +#define rCCK0_RxHP 0xa14 + +/* Timing recovery & Channel estimation threshold */ +#define rCCK0_DSPParameter1 0xa18 +#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ +#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now */ +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 /* 0xa57 */ +#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ +#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ + +/* */ +/* PageB(0xB00) */ +/* */ +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rConfig_Pmpd_AntB 0xb98 +#define rAPK 0xbd8 + +/* */ +/* 6. PageC(0xC00) */ +/* */ +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +/* RxIQ DC offset, Rx digital filter, DC notch filter */ +#define rOFDM0_XARxAFE 0xc10 +#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 /*PD,BW & SBD DM tune init gain*/ +#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ +#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ +#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ + +#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ +#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ +#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ +#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ + +#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 + + +/* */ +/* 7. PageD(0xD00) */ +/* */ +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 /* No setting now */ +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ +#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ +#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ + +#define rOFDM_ShortCFOAB 0xdac /* No setting now */ +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +/* */ +/* 8. PageE(0xE00) */ +/* */ +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + +/* */ +/* 7. RF Register 0x00-0x2E (RF 8256) */ +/* RF-0222D 0x00-3F */ +/* */ +/* Zebra1 */ +#define rZebra1_HSSIEnable 0x0 /* Useless now */ +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 /* RF channel switch */ + +/* endif */ +#define rZebra1_TxGain 0x8 /* Useless now */ +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +/* Zebra4 */ +#define rGlobalCtrl 0 /* Useless now */ +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +/* RTL8258 */ +#define rRTL8258_TxLPF 0x11 /* Useless now */ +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +/* */ +/* RL6052 Register definition */ +/* */ +#define RF_AC 0x00 /* */ + +#define RF_IQADJ_G1 0x01 /* */ +#define RF_IQADJ_G2 0x02 /* */ + +#define RF_POW_TRSW 0x05 /* */ + +#define RF_GAIN_RX 0x06 /* */ +#define RF_GAIN_TX 0x07 /* */ + +#define RF_TXM_IDAC 0x08 /* */ +#define RF_IPA_G 0x09 /* */ +#define RF_TXBIAS_G 0x0A +#define RF_TXPA_AG 0x0B +#define RF_IPA_A 0x0C /* */ +#define RF_TXBIAS_A 0x0D +#define RF_BS_PA_APSET_G9_G11 0x0E +#define RF_BS_IQGEN 0x0F /* */ + +#define RF_MODE1 0x10 /* */ +#define RF_MODE2 0x11 /* */ + +#define RF_RX_AGC_HP 0x12 /* */ +#define RF_TX_AGC 0x13 /* */ +#define RF_BIAS 0x14 /* */ +#define RF_IPA 0x15 /* */ +#define RF_TXBIAS 0x16 +#define RF_POW_ABILITY 0x17 /* */ +#define RF_CHNLBW 0x18 /* RF channel and BW switch */ +#define RF_TOP 0x19 /* */ + +#define RF_RX_G1 0x1A /* */ +#define RF_RX_G2 0x1B /* */ + +#define RF_RX_BB2 0x1C /* */ +#define RF_RX_BB1 0x1D /* */ + +#define RF_RCK1 0x1E /* */ +#define RF_RCK2 0x1F /* */ + +#define RF_TX_G1 0x20 /* */ +#define RF_TX_G2 0x21 /* */ +#define RF_TX_G3 0x22 /* */ + +#define RF_TX_BB1 0x23 /* */ + +#define RF_T_METER_92D 0x42 /* */ +#define RF_T_METER_88E 0x42 /* */ +#define RF_T_METER 0x24 /* */ + +#define RF_SYN_G1 0x25 /* RF TX Power control */ +#define RF_SYN_G2 0x26 /* RF TX Power control */ +#define RF_SYN_G3 0x27 /* RF TX Power control */ +#define RF_SYN_G4 0x28 /* RF TX Power control */ +#define RF_SYN_G5 0x29 /* RF TX Power control */ +#define RF_SYN_G6 0x2A /* RF TX Power control */ +#define RF_SYN_G7 0x2B /* RF TX Power control */ +#define RF_SYN_G8 0x2C /* RF TX Power control */ + +#define RF_RCK_OS 0x30 /* RF TX PA control */ +#define RF_TXPA_G1 0x31 /* RF TX PA control */ +#define RF_TXPA_G2 0x32 /* RF TX PA control */ +#define RF_TXPA_G3 0x33 /* RF TX PA control */ +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C /* */ +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_WE_LUT 0xEF + + +/* */ +/* Bit Mask */ +/* */ +/* 1. Page1(0x100) */ +#define bBBResetB 0x100 /* Useless now? */ +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) \ + ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +/* 2. Page8(0x800) */ +#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 /* Useless now */ +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bAntennaSelect 0x0300 + +#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 /* Useless now */ +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf /* Reg0x814 */ +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 /* T2R */ +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 /* change gain at continue Tx */ +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ +#define b3WireDataLength 0x800 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 /* Useless now */ +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ + +#define bRFSI_TRSW 0x20 /* Useless now */ +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +#define bLSSIReadAddress 0x7f800000 /* T65 RF */ + +#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ + +#define bLSSIReadBackData 0xfffff /* T65 RF */ + +#define bLSSIReadOKFlag 0x1000 /* Useless now */ +#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ +#define bADClkPhase 0x4000000 + +#define b80MClkDelay 0x18000000 /* Useless */ +#define bAFEWatchDogEnable 0x20000000 + +/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ +#define bXtalCap01 0xc0000000 +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 /* Useless */ +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +/* 3. Page9(0x900) */ +#define bOFDMTxSC 0x30000000 /* Useless */ +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff /* reset debug page and HWord, LWord */ +#define bDebugItem 0xff /* reset debug page and LWord */ +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +/* 4. PageA(0xA00) */ +#define bCCKBBMode 0x3 /* Useless */ +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */ + +#define bCCKScramble 0x8 /* Useless */ +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ +#define bCCKFixedRxAGC 0x8000 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +/* 5. PageC(0xC00) */ +#define bNumOfSTF 0x3 /* Useless */ +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 /* threshold for high power */ +#define bRSSI_Gen 0x7f000000 /* threshold for ant diversity */ +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +/* 6. PageE(0xE00) */ +#define bSTBCEn 0x4 /* Useless */ +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 /* total */ +#define bShortCFOFLength 11 /* fraction */ +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf /* Useless */ +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 /* Useless */ +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 /* Useless */ +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +/* Rx Pseduo noise */ +#define bRxPesudoNoiseOn 0x20000000 /* Useless */ +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +/* 7. RF Register */ +/* Zebra1 */ +#define bZebra1_HSSIEnable 0x8 /* Useless */ +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +/* Zebra4 */ +#define bRTL8256RegModeCtrl1 0x100 /* Useless */ +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +/* RTL8258 */ +#define bRTL8258_TxLPFBW 0xc /* Useless */ +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +/* */ +/* Other Definition */ +/* */ + +/* byte endable for sb_write */ +#define bByte0 0x1 /* Useless */ +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +/* for PutRegsetting & GetRegSetting BitMask */ +#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMask12Bits 0xfff +#define bMaskH4Bits 0xf0000000 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f + +/* for PutRFRegsetting & GetRFRegSetting BitMask */ +#define bRFRegOffsetMask 0xfffff + +#define bEnable 0x1 /* Useless */ +#define bDisable 0x0 + +#define LeftAntenna 0x0 /* Useless */ +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 /* 500ms Useless */ +#define tUpdateRxCounter 100 /* 100ms */ + +#define rateCCK 0 /* Useless */ +#define rateOFDM 1 +#define rateHT 2 + +/* define Register-End */ +#define bPMAC_End 0x1ff /* Useless */ +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +#define bPMACControl 0x0 /* Useless */ +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 /* Useless */ +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +/*--------------------------Define Parameters-------------------------------*/ + + +#endif diff --git a/drivers/staging/rtl8188eu/include/hal8188e_rate_adaptive.h b/drivers/staging/rtl8188eu/include/hal8188e_rate_adaptive.h new file mode 100644 index 0000000..5b59c25 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/hal8188e_rate_adaptive.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_RA_H +#define __INC_RA_H +/* + * Copyright (c) Realtek Semiconductor Corp. All rights reserved. + * + * Module Name: + * RateAdaptive.h + * + * Abstract: + * Prototype of RA and related data structure. + * + * Major Change History: + * When Who What + * ---------- --------------- ------------------------------- + * 2011-08-12 Page Create. + */ + +/* Rate adaptive define */ +#define PERENTRY 23 +#define RETRYSIZE 5 +#define RATESIZE 28 +#define TX_RPT2_ITEM_SIZE 8 + +/* */ +/* TX report 2 format in Rx desc */ +/* */ +#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 9) +#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 32) +#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) + +#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) \ + LE_BITS_TO_4BYTE(__pAddr, 0, 16) +#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) \ + LE_BITS_TO_1BYTE(__pAddr+2, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) \ + LE_BITS_TO_1BYTE(__pAddr+3, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) \ + LE_BITS_TO_1BYTE(__pAddr+4, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) \ + LE_BITS_TO_1BYTE(__pAddr+4+1, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) \ + LE_BITS_TO_1BYTE(__pAddr+4+2, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) \ + LE_BITS_TO_1BYTE(__pAddr+4+3, 0, 8) + +/* End rate adaptive define */ + +int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm); + +int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 MacID); + +u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 MacID); + +u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 MacID); + +u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 MacID); +void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 MacID, + u8 RateID, u32 RateMask, + u8 SGIEnable); + +void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid, + u8 rssi); + +void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm, + u8 *txrpt_buf, u16 txrpt_len, + u32 validentry0, u32 validentry1); + +void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime); + +#endif diff --git a/drivers/staging/rtl8188eu/include/hal_com.h b/drivers/staging/rtl8188eu/include/hal_com.h new file mode 100644 index 0000000..428a2a9 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/hal_com.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __HAL_COMMON_H__ +#define __HAL_COMMON_H__ + +/* */ +/* Rate Definition */ +/* */ +/* CCK */ +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +/* OFDM */ +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +/* MCS 1 Spatial Stream */ +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +/* MCS 2 Spatial Stream */ +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 + +/* CCK */ +#define RATE_1M BIT(0) +#define RATE_2M BIT(1) +#define RATE_5_5M BIT(2) +#define RATE_11M BIT(3) +/* OFDM */ +#define RATE_6M BIT(4) +#define RATE_9M BIT(5) +#define RATE_12M BIT(6) +#define RATE_18M BIT(7) +#define RATE_24M BIT(8) +#define RATE_36M BIT(9) +#define RATE_48M BIT(10) +#define RATE_54M BIT(11) +/* MCS 1 Spatial Stream */ +#define RATE_MCS0 BIT(12) +#define RATE_MCS1 BIT(13) +#define RATE_MCS2 BIT(14) +#define RATE_MCS3 BIT(15) +#define RATE_MCS4 BIT(16) +#define RATE_MCS5 BIT(17) +#define RATE_MCS6 BIT(18) +#define RATE_MCS7 BIT(19) +/* MCS 2 Spatial Stream */ +#define RATE_MCS8 BIT(20) +#define RATE_MCS9 BIT(21) +#define RATE_MCS10 BIT(22) +#define RATE_MCS11 BIT(23) +#define RATE_MCS12 BIT(24) +#define RATE_MCS13 BIT(25) +#define RATE_MCS14 BIT(26) +#define RATE_MCS15 BIT(27) + +/* ALL CCK Rate */ +#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) +#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \ + RATR_24M | RATR_36M | RATR_48M | RATR_54M) +#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ + RATR_MCS3 | RATR_MCS4 | RATR_MCS5|RATR_MCS6 | \ + RATR_MCS7) +#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ + RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ + RATR_MCS14 | RATR_MCS15) + +/*------------------------------ Tx Desc definition Macro --------------------*/ +/* pragma mark -- Tx Desc related definition. -- */ +/* Rate */ +/* CCK Rates, TxHT = 0 */ +#define DESC_RATE1M 0x00 +#define DESC_RATE2M 0x01 +#define DESC_RATE5_5M 0x02 +#define DESC_RATE11M 0x03 + +/* OFDM Rates, TxHT = 0 */ +#define DESC_RATE6M 0x04 +#define DESC_RATE9M 0x05 +#define DESC_RATE12M 0x06 +#define DESC_RATE18M 0x07 +#define DESC_RATE24M 0x08 +#define DESC_RATE36M 0x09 +#define DESC_RATE48M 0x0a +#define DESC_RATE54M 0x0b + +/* MCS Rates, TxHT = 1 */ +#define DESC_RATEMCS0 0x0c +#define DESC_RATEMCS1 0x0d +#define DESC_RATEMCS2 0x0e +#define DESC_RATEMCS3 0x0f +#define DESC_RATEMCS4 0x10 +#define DESC_RATEMCS5 0x11 +#define DESC_RATEMCS6 0x12 +#define DESC_RATEMCS7 0x13 +#define DESC_RATEMCS8 0x14 +#define DESC_RATEMCS9 0x15 +#define DESC_RATEMCS10 0x16 +#define DESC_RATEMCS11 0x17 +#define DESC_RATEMCS12 0x18 +#define DESC_RATEMCS13 0x19 +#define DESC_RATEMCS14 0x1a +#define DESC_RATEMCS15 0x1b +#define DESC_RATEMCS15_SG 0x1c +#define DESC_RATEMCS32 0x20 + +/* 1 Byte long (in unit of TU) */ +#define REG_P2P_CTWIN 0x0572 +#define REG_NOA_DESC_SEL 0x05CF +#define REG_NOA_DESC_DURATION 0x05E0 +#define REG_NOA_DESC_INTERVAL 0x05E4 +#define REG_NOA_DESC_START 0x05E8 +#define REG_NOA_DESC_COUNT 0x05EC + +#include "HalVerDef.h" +void dump_chip_info(struct HAL_VERSION ChipVersion); + + +/* return the final channel plan decision */ +u8 hal_com_get_channel_plan(struct adapter *padapter, + u8 hw_channel_plan, + u8 sw_channel_plan, + u8 def_channel_plan, + bool AutoLoadFail +); + +u8 MRateToHwRate(u8 rate); + +void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg); + +bool Hal_MappingOutPipe(struct adapter *pAdapter, u8 NumOutPipe); + +void hal_init_macaddr(struct adapter *adapter); +#endif /* __HAL_COMMON_H__ */ diff --git a/drivers/staging/rtl8188eu/include/hal_intf.h b/drivers/staging/rtl8188eu/include/hal_intf.h new file mode 100644 index 0000000..e5be27a --- /dev/null +++ b/drivers/staging/rtl8188eu/include/hal_intf.h @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __HAL_INTF_H__ +#define __HAL_INTF_H__ + +#include <osdep_service.h> +#include <drv_types.h> +#include <hal8188e_phy_cfg.h> + +enum RTL871X_HCI_TYPE { + RTW_PCIE = BIT(0), + RTW_USB = BIT(1), + RTW_SDIO = BIT(2), + RTW_GSPI = BIT(3), +}; + +enum _CHIP_TYPE { + NULL_CHIP_TYPE, + RTL8712_8188S_8191S_8192S, + RTL8188C_8192C, + RTL8192D, + RTL8723A, + RTL8188E, + MAX_CHIP_TYPE +}; + +enum hw_variables { + HW_VAR_MEDIA_STATUS, + HW_VAR_MEDIA_STATUS1, + HW_VAR_SET_OPMODE, + HW_VAR_MAC_ADDR, + HW_VAR_BSSID, + HW_VAR_INIT_RTS_RATE, + HW_VAR_BASIC_RATE, + HW_VAR_TXPAUSE, + HW_VAR_BCN_FUNC, + HW_VAR_CORRECT_TSF, + HW_VAR_CHECK_BSSID, + HW_VAR_MLME_DISCONNECT, + HW_VAR_MLME_SITESURVEY, + HW_VAR_MLME_JOIN, + HW_VAR_BEACON_INTERVAL, + HW_VAR_SLOT_TIME, + HW_VAR_RESP_SIFS, + HW_VAR_ACK_PREAMBLE, + HW_VAR_SEC_CFG, + HW_VAR_BCN_VALID, + HW_VAR_DM_FUNC_OP, + HW_VAR_DM_FUNC_SET, + HW_VAR_DM_FUNC_CLR, + HW_VAR_CAM_EMPTY_ENTRY, + HW_VAR_CAM_INVALID_ALL, + HW_VAR_CAM_WRITE, + HW_VAR_CAM_READ, + HW_VAR_AC_PARAM_VO, + HW_VAR_AC_PARAM_VI, + HW_VAR_AC_PARAM_BE, + HW_VAR_AC_PARAM_BK, + HW_VAR_ACM_CTRL, + HW_VAR_AMPDU_MIN_SPACE, + HW_VAR_AMPDU_FACTOR, + HW_VAR_RXDMA_AGG_PG_TH, + HW_VAR_SET_RPWM, + HW_VAR_H2C_FW_PWRMODE, + HW_VAR_H2C_FW_JOINBSSRPT, + HW_VAR_FWLPS_RF_ON, + HW_VAR_H2C_FW_P2P_PS_OFFLOAD, + HW_VAR_TDLS_WRCR, + HW_VAR_TDLS_INIT_CH_SEN, + HW_VAR_TDLS_RS_RCR, + HW_VAR_TDLS_DONE_CH_SEN, + HW_VAR_INITIAL_GAIN, + HW_VAR_TRIGGER_GPIO_0, + HW_VAR_BT_SET_COEXIST, + HW_VAR_BT_ISSUE_DELBA, + HW_VAR_CURRENT_ANTENNA, + HW_VAR_ANTENNA_DIVERSITY_LINK, + HW_VAR_ANTENNA_DIVERSITY_SELECT, + HW_VAR_SWITCH_EPHY_WoWLAN, + HW_VAR_EFUSE_USAGE, + HW_VAR_EFUSE_BYTES, + HW_VAR_EFUSE_BT_USAGE, + HW_VAR_EFUSE_BT_BYTES, + HW_VAR_FIFO_CLEARN_UP, + HW_VAR_CHECK_TXBUF, + HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, + * power control for MAC only + */ + /* The valid upper nav range for the HW updating, if the true value is + * larger than the upper range, the HW won't update it. + */ + /* Unit in microsecond. 0 means disable this function. */ + HW_VAR_NAV_UPPER, + HW_VAR_RPT_TIMER_SETTING, + HW_VAR_TX_RPT_MAX_MACID, + HW_VAR_H2C_MEDIA_STATUS_RPT, + HW_VAR_CHK_HI_QUEUE_EMPTY, +}; + +enum hal_def_variable { + HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, + HAL_DEF_IS_SUPPORT_ANT_DIV, + HAL_DEF_CURRENT_ANTENNA, + HAL_DEF_DRVINFO_SZ, + HAL_DEF_MAX_RECVBUF_SZ, + HAL_DEF_RX_PACKET_OFFSET, + HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */ + HAL_DEF_DBG_DM_FUNC,/* for dbg */ + HAL_DEF_RA_DECISION_RATE, + HAL_DEF_RA_SGI, + HAL_DEF_PT_PWR_STATUS, + HW_VAR_MAX_RX_AMPDU_FACTOR, + HW_DEF_RA_INFO_DUMP, + HAL_DEF_DBG_DUMP_TXPKT, + HW_DEF_FA_CNT_DUMP, + HW_DEF_ODM_DBG_FLAG, +}; + +enum hal_odm_variable { + HAL_ODM_STA_INFO, + HAL_ODM_P2P_STATE, + HAL_ODM_WIFI_DISPLAY_STATE, +}; + +enum hal_intf_ps_func { + HAL_USB_SELECT_SUSPEND, + HAL_MAX_ID, +}; + +enum rt_eeprom_type { + EEPROM_93C46, + EEPROM_93C56, + EEPROM_BOOT_EFUSE, +}; + +#define RF_CHANGE_BY_INIT 0 +#define RF_CHANGE_BY_IPS BIT(28) +#define RF_CHANGE_BY_PS BIT(29) +#define RF_CHANGE_BY_HW BIT(30) +#define RF_CHANGE_BY_SW BIT(31) + +enum hardware_type { + HARDWARE_TYPE_RTL8188EU, + HARDWARE_TYPE_MAX, +}; + +#define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv) + +#define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse) + +void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level); +u32 rtl8188eu_hal_deinit(struct adapter *Adapter); +u32 rtl8188eu_hal_init(struct adapter *Adapter); +void rtw_hal_def_value_init(struct adapter *padapter); + +void rtw_hal_free_data(struct adapter *padapter); + +void rtw_hal_dm_init(struct adapter *padapter); +void rtw_hal_sw_led_init(struct adapter *padapter); +void rtw_hal_sw_led_deinit(struct adapter *padapter); + +u32 rtw_hal_power_on(struct adapter *padapter); +uint rtw_hal_init(struct adapter *padapter); +uint rtw_hal_deinit(struct adapter *padapter); +void rtw_hal_stop(struct adapter *padapter); +void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val); +void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val); + +void rtw_hal_chip_configure(struct adapter *padapter); +void rtw_hal_read_chip_info(struct adapter *padapter); +void rtw_hal_read_chip_version(struct adapter *padapter); + +u8 rtw_hal_get_def_var(struct adapter *padapter, + enum hal_def_variable eVariable, void *pValue); + +void rtw_hal_set_odm_var(struct adapter *padapter, + enum hal_odm_variable eVariable, void *pValue1, + bool bSet); + +u32 rtw_hal_inirp_init(struct adapter *padapter); +void rtw_hal_inirp_deinit(struct adapter *padapter); +void usb_intf_stop(struct adapter *padapter); + +s32 rtw_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtw_hal_mgnt_xmit(struct adapter *padapter, + struct xmit_frame *pmgntframe); + +s32 rtw_hal_init_xmit_priv(struct adapter *padapter); + +int rtw_hal_init_recv_priv(struct adapter *padapter); +void rtw_hal_free_recv_priv(struct adapter *padapter); + +void rtw_hal_update_ra_mask(struct adapter *padapter, u32 mac_id, u8 level); +void rtw_hal_add_ra_tid(struct adapter *adapt, u32 bitmap, u8 arg, u8 level); +void rtw_hal_clone_data(struct adapter *dst_adapt, + struct adapter *src_adapt); + +void rtw_hal_bcn_related_reg_setting(struct adapter *padapter); + +u32 rtw_hal_read_rfreg(struct adapter *padapter, enum rf_radio_path eRFPath, + u32 RegAddr, u32 BitMask); + +void rtw_hal_set_bwmode(struct adapter *padapter, + enum ht_channel_width Bandwidth, u8 Offset); +void rtw_hal_set_chan(struct adapter *padapter, u8 channel); +void rtw_hal_dm_watchdog(struct adapter *padapter); + +u8 rtw_hal_antdiv_before_linked(struct adapter *padapter); +void rtw_hal_antdiv_rssi_compared(struct adapter *padapter, + struct wlan_bssid_ex *dst, + struct wlan_bssid_ex *src); + +void rtw_hal_sreset_init(struct adapter *padapter); + +void rtw_hal_notch_filter(struct adapter *adapter, bool enable); + +void indicate_wx_scan_complete_event(struct adapter *padapter); +u8 rtw_do_join(struct adapter *padapter); + +#endif /* __HAL_INTF_H__ */ diff --git a/drivers/staging/rtl8188eu/include/ieee80211.h b/drivers/staging/rtl8188eu/include/ieee80211.h new file mode 100644 index 0000000..62e3844 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/ieee80211.h @@ -0,0 +1,783 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __IEEE80211_H +#define __IEEE80211_H + +#include <osdep_service.h> +#include <drv_types.h> +#include "wifi.h" +#include <linux/wireless.h> + +#define MGMT_QUEUE_NUM 5 + +#define ETH_ALEN 6 +#define ETH_TYPE_LEN 2 +#define PAYLOAD_TYPE_LEN 1 + +#ifdef CPTCFG_88EU_AP_MODE + +#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) + +/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ +enum { + RTL871X_HOSTAPD_FLUSH = 1, + RTL871X_HOSTAPD_ADD_STA = 2, + RTL871X_HOSTAPD_REMOVE_STA = 3, + RTL871X_HOSTAPD_GET_INFO_STA = 4, + /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */ + RTL871X_HOSTAPD_GET_WPAIE_STA = 5, + RTL871X_SET_ENCRYPTION = 6, + RTL871X_GET_ENCRYPTION = 7, + RTL871X_HOSTAPD_SET_FLAGS_STA = 8, + RTL871X_HOSTAPD_GET_RID = 9, + RTL871X_HOSTAPD_SET_RID = 10, + RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11, + RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12, + RTL871X_HOSTAPD_MLME = 13, + RTL871X_HOSTAPD_SCAN_REQ = 14, + RTL871X_HOSTAPD_STA_CLEAR_STATS = 15, + RTL871X_HOSTAPD_SET_BEACON = 16, + RTL871X_HOSTAPD_SET_WPS_BEACON = 17, + RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18, + RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19, + RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20, + RTL871X_HOSTAPD_SET_MACADDR_ACL = 21, + RTL871X_HOSTAPD_ACL_ADD_STA = 22, + RTL871X_HOSTAPD_ACL_REMOVE_STA = 23, +}; + +/* STA flags */ +#define WLAN_STA_AUTH BIT(0) +#define WLAN_STA_ASSOC BIT(1) +#define WLAN_STA_PS BIT(2) +#define WLAN_STA_TIM BIT(3) +#define WLAN_STA_PERM BIT(4) +#define WLAN_STA_AUTHORIZED BIT(5) +#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ +#define WLAN_STA_SHORT_PREAMBLE BIT(7) +#define WLAN_STA_PREAUTH BIT(8) +#define WLAN_STA_WME BIT(9) +#define WLAN_STA_MFP BIT(10) +#define WLAN_STA_HT BIT(11) +#define WLAN_STA_WPS BIT(12) +#define WLAN_STA_MAYBE_WPS BIT(13) +#define WLAN_STA_NONERP BIT(31) + +#endif + +#define IEEE_CMD_SET_WPA_PARAM 1 +#define IEEE_CMD_SET_WPA_IE 2 +#define IEEE_CMD_SET_ENCRYPTION 3 +#define IEEE_CMD_MLME 4 + +#define IEEE_PARAM_WPA_ENABLED 1 +#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 +#define IEEE_PARAM_DROP_UNENCRYPTED 3 +#define IEEE_PARAM_PRIVACY_INVOKED 4 +#define IEEE_PARAM_AUTH_ALGS 5 +#define IEEE_PARAM_IEEE_802_1X 6 +#define IEEE_PARAM_WPAX_SELECT 7 + +#define AUTH_ALG_OPEN_SYSTEM 0x1 +#define AUTH_ALG_SHARED_KEY 0x2 +#define AUTH_ALG_LEAP 0x00000004 + +#define IEEE_MLME_STA_DEAUTH 1 +#define IEEE_MLME_STA_DISASSOC 2 + +#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 +#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 +#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 +#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 +#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 +#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 + + +#define IEEE_CRYPT_ALG_NAME_LEN 16 + +#define WPA_CIPHER_NONE BIT(0) +#define WPA_CIPHER_WEP40 BIT(1) +#define WPA_CIPHER_WEP104 BIT(2) +#define WPA_CIPHER_TKIP BIT(3) +#define WPA_CIPHER_CCMP BIT(4) + + + +#define WPA_SELECTOR_LEN 4 +extern u8 RTW_WPA_OUI_TYPE[]; +extern u8 WPA_AUTH_KEY_MGMT_NONE[]; +extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +extern u8 WPA_CIPHER_SUITE_NONE[]; +extern u8 WPA_CIPHER_SUITE_WEP40[]; +extern u8 WPA_CIPHER_SUITE_TKIP[]; +extern u8 WPA_CIPHER_SUITE_WRAP[]; +extern u8 WPA_CIPHER_SUITE_CCMP[]; +extern u8 WPA_CIPHER_SUITE_WEP104[]; + + +#define RSN_HEADER_LEN 4 +#define RSN_SELECTOR_LEN 4 + +extern u16 RSN_VERSION_BSD; +extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +extern u8 RSN_CIPHER_SUITE_NONE[]; +extern u8 RSN_CIPHER_SUITE_WEP40[]; +extern u8 RSN_CIPHER_SUITE_TKIP[]; +extern u8 RSN_CIPHER_SUITE_WRAP[]; +extern u8 RSN_CIPHER_SUITE_CCMP[]; +extern u8 RSN_CIPHER_SUITE_WEP104[]; + +enum ratr_table_mode { + RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */ + RATR_INX_WIRELESS_NG = 1, /* GN or N */ + RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */ + RATR_INX_WIRELESS_N = 3, + RATR_INX_WIRELESS_GB = 4, + RATR_INX_WIRELESS_G = 5, + RATR_INX_WIRELESS_B = 6, + RATR_INX_WIRELESS_MC = 7, + RATR_INX_WIRELESS_AC_N = 8, +}; + +enum NETWORK_TYPE { + WIRELESS_INVALID = 0, + /* Sub-Element */ + WIRELESS_11B = BIT(0), /* tx:cck only, rx:cck only, hw: cck */ + WIRELESS_11G = BIT(1), /* tx:ofdm only, rx:ofdm & cck, hw:cck & ofdm*/ + WIRELESS_11A = BIT(2), /* tx:ofdm only, rx: ofdm only, hw:ofdm only */ + WIRELESS_11_24N = BIT(3), /* tx:MCS only, rx:MCS & cck, hw:MCS & cck */ + WIRELESS_11_5N = BIT(4), /* tx:MCS only, rx:MCS & ofdm, hw:ofdm only */ + WIRELESS_AC = BIT(6), + + /* Combination */ + /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */ + WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), + /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */ + WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), + /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ + WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), + /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ + WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), + /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ + WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | + WIRELESS_11_5N), + WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | + WIRELESS_11_24N | WIRELESS_11_5N), +}; + +#define SUPPORTED_24G_NETTYPE_MSK \ + (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N) +#define SUPPORTED_5G_NETTYPE_MSK \ + (WIRELESS_11A | WIRELESS_11_5N) + +#define IsSupported24G(NetType) \ + ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? true : false) +#define IsSupported5G(NetType) \ + ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? true : false) + +#define IsEnableHWCCK(NetType) \ + IsSupported24G(NetType) +#define IsEnableHWOFDM(NetType) \ + ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | \ + SUPPORTED_5G_NETTYPE_MSK) ? true : false) + +#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) +#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) +#define IsSupportedRxMCS(NetType) IsEnableHWOFDM(NetType) + +#define IsSupportedTxCCK(NetType) \ + ((NetType) & (WIRELESS_11B) ? true : false) +#define IsSupportedTxOFDM(NetType) \ + ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? true : false) +#define IsSupportedTxMCS(NetType) \ + ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? true : false) + + +struct ieee_param { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + union { + struct { + u8 name; + u32 value; + } wpa_param; + struct { + u32 len; + u8 reserved[32]; + u8 data[0]; + } wpa_ie; + struct { + int command; + int reason_code; + } mlme; + struct { + u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; + u8 set_tx; + u32 err; + u8 idx; + u8 seq[8]; /* sequence counter (set: RX, get: TX) */ + u16 key_len; + u8 key[0]; + } crypt; +#ifdef CPTCFG_88EU_AP_MODE + struct { + u16 aid; + u16 capability; + int flags; + u8 tx_supp_rates[16]; + struct ieee80211_ht_cap ht_cap; + } add_sta; + struct { + u8 reserved[2];/* for set max_num_sta */ + u8 buf[0]; + } bcn_ie; +#endif + + } u; +}; + +#ifdef CPTCFG_88EU_AP_MODE +struct ieee_param_ex { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + u8 data[0]; +}; + +struct sta_data { + u16 aid; + u16 capability; + int flags; + u32 sta_set; + u8 tx_supp_rates[16]; + u32 tx_supp_rates_len; + struct ieee80211_ht_cap ht_cap; + u64 rx_pkts; + u64 rx_bytes; + u64 rx_drops; + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; +}; +#endif + +#define IEEE80211_DATA_LEN 2304 +/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section + * 6.2.1.1.2. + + * The figure in section 7.1.2 suggests a body size of up to 2312 + * bytes is allowed, which is a bit confusing, I suspect this + * represents the 2304 bytes of real data, plus a possible 8 bytes of + * WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) + */ + + +#define IEEE80211_HLEN 30 +#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) + + +/* this is stolen from ipw2200 driver */ +#define IEEE_IBSS_MAC_HASH_SIZE 31 + +enum eap_type { + EAP_PACKET = 0, + EAPOL_START, + EAPOL_LOGOFF, + EAPOL_KEY, + EAPOL_ENCAP_ASF_ALERT +}; + +#define IEEE80211_3ADDR_LEN 24 +#define IEEE80211_4ADDR_LEN 30 +#define IEEE80211_FCS_LEN 4 + +#define MIN_FRAG_THRESHOLD 256U +#define MAX_FRAG_THRESHOLD 2346U + +/* sequence control field */ +#define RTW_IEEE80211_SCTL_FRAG 0x000F +#define RTW_IEEE80211_SCTL_SEQ 0xFFF0 + + +#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) +#define RTW_ERP_INFO_USE_PROTECTION BIT(1) +#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) + +/* QoS, QOS */ +#define NORMAL_ACK 0 +#define NO_ACK 1 +#define NON_EXPLICIT_ACK 2 +#define BLOCK_ACK 3 + +#ifndef ETH_P_PAE +#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#endif /* ETH_P_PAE */ + +#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ + +#define ETH_P_ECONET 0x0018 + +#ifndef ETH_P_80211_RAW +#define ETH_P_80211_RAW (ETH_P_ECONET + 1) +#endif + +/* IEEE 802.11 defines */ + +#define P80211_OUI_LEN 3 + +struct ieee80211_snap_hdr { + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ +} __packed; + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) + +#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) +#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ) + +/* Non standard? Not in <linux/ieee80211.h> */ +#define WLAN_REASON_EXPIRATION_CHK 65535 + +#define IEEE80211_MGMT_HDR_LEN 24 +#define IEEE80211_DATA_HDR3_LEN 24 +#define IEEE80211_DATA_HDR4_LEN 30 + +#define IEEE80211_CCK_MODULATION BIT(0) +#define IEEE80211_OFDM_MODULATION BIT(1) + +#define IEEE80211_24GHZ_BAND BIT(0) +#define IEEE80211_52GHZ_BAND BIT(1) + +#define IEEE80211_CCK_RATE_LEN 4 +#define IEEE80211_NUM_OFDM_RATESLEN 8 + + +#define IEEE80211_CCK_RATE_1MB 0x02 +#define IEEE80211_CCK_RATE_2MB 0x04 +#define IEEE80211_CCK_RATE_5MB 0x0B +#define IEEE80211_CCK_RATE_11MB 0x16 +#define IEEE80211_OFDM_RATE_LEN 8 +#define IEEE80211_OFDM_RATE_6MB 0x0C +#define IEEE80211_OFDM_RATE_9MB 0x12 +#define IEEE80211_OFDM_RATE_12MB 0x18 +#define IEEE80211_OFDM_RATE_18MB 0x24 +#define IEEE80211_OFDM_RATE_24MB 0x30 +#define IEEE80211_OFDM_RATE_36MB 0x48 +#define IEEE80211_OFDM_RATE_48MB 0x60 +#define IEEE80211_OFDM_RATE_54MB 0x6C +#define IEEE80211_BASIC_RATE_MASK 0x80 + +#define IEEE80211_CCK_RATE_1MB_MASK BIT(0) +#define IEEE80211_CCK_RATE_2MB_MASK BIT(1) +#define IEEE80211_CCK_RATE_5MB_MASK BIT(2) +#define IEEE80211_CCK_RATE_11MB_MASK BIT(3) +#define IEEE80211_OFDM_RATE_6MB_MASK BIT(4) +#define IEEE80211_OFDM_RATE_9MB_MASK BIT(5) +#define IEEE80211_OFDM_RATE_12MB_MASK BIT(6) +#define IEEE80211_OFDM_RATE_18MB_MASK BIT(7) +#define IEEE80211_OFDM_RATE_24MB_MASK BIT(8) +#define IEEE80211_OFDM_RATE_36MB_MASK BIT(9) +#define IEEE80211_OFDM_RATE_48MB_MASK BIT(10) +#define IEEE80211_OFDM_RATE_54MB_MASK BIT(11) + +#define IEEE80211_CCK_RATES_MASK 0x0000000F +#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ + IEEE80211_CCK_RATE_2MB_MASK) +#define IEEE80211_CCK_DEFAULT_RATES_MASK \ + (IEEE80211_CCK_BASIC_RATES_MASK | \ + IEEE80211_CCK_RATE_5MB_MASK | \ + IEEE80211_CCK_RATE_11MB_MASK) + +#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 +#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ + IEEE80211_OFDM_RATE_12MB_MASK | \ + IEEE80211_OFDM_RATE_24MB_MASK) +#define IEEE80211_OFDM_DEFAULT_RATES_MASK \ + (IEEE80211_OFDM_BASIC_RATES_MASK | \ + IEEE80211_OFDM_RATE_9MB_MASK | \ + IEEE80211_OFDM_RATE_18MB_MASK | \ + IEEE80211_OFDM_RATE_36MB_MASK | \ + IEEE80211_OFDM_RATE_48MB_MASK | \ + IEEE80211_OFDM_RATE_54MB_MASK) + +#define IEEE80211_NUM_OFDM_RATES 8 +#define IEEE80211_NUM_CCK_RATES 4 +#define IEEE80211_OFDM_SHIFT_MASK_A 4 + +/* IEEE 802.11 requires that STA supports concurrent reception of at least + * three fragmented frames. This define can be increased to support more + * concurrent frames, but it should be noted that each entry can consume about + * 2 kB of RAM and increasing cache size will slow down frame reassembly. + */ +#define IEEE80211_FRAG_CACHE_LEN 4 + +#define SEC_KEY_1 BIT(0) +#define SEC_KEY_2 BIT(1) +#define SEC_KEY_3 BIT(2) +#define SEC_KEY_4 BIT(3) +#define SEC_ACTIVE_KEY BIT(4) +#define SEC_AUTH_MODE BIT(5) +#define SEC_UNICAST_GROUP BIT(6) +#define SEC_LEVEL BIT(7) +#define SEC_ENABLED BIT(8) + +#define SEC_LEVEL_0 0 /* None */ +#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ +#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ +#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ +#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ + +#define WEP_KEYS 4 +#define WEP_KEY_LEN 13 + +/* SWEEP TABLE ENTRIES NUMBER*/ +#define MAX_SWEEP_TAB_ENTRIES 42 +#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 +/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs + * only use 8, and then use extended rates for the remaining supported + * rates. Other APs, however, stick all of their supported rates on the + * main rates information element... + */ +#define MAX_RATES_LENGTH ((u8)12) +#define MAX_RATES_EX_LENGTH ((u8)16) +#define MAX_NETWORK_COUNT 128 +#define MAX_CHANNEL_NUMBER 161 +#define IEEE80211_SOFTMAC_SCAN_TIME 400 +/* HZ / 2) */ +#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) + +#define CRC_LENGTH 4U + +#define MAX_WPA_IE_LEN (256) +#define MAX_WPS_IE_LEN (512) +#define MAX_P2P_IE_LEN (256) +#define MAX_WFD_IE_LEN (128) + +#define NETWORK_EMPTY_ESSID BIT(0) +#define NETWORK_HAS_OFDM BIT(1) +#define NETWORK_HAS_CCK BIT(2) + +#define IW_ESSID_MAX_SIZE 32 +/* + * join_res: + * -1: authentication fail + * -2: association fail + * > 0: TID + */ + +enum ieee80211_state { + /* the card is not linked at all */ + IEEE80211_NOLINK = 0, + + /* IEEE80211_ASSOCIATING* are for BSS client mode + * the driver shall not perform RX filtering unless + * the state is LINKED. + * The driver shall just check for the state LINKED and + * defaults to NOLINK for ALL the other states (including + * LINKED_SCANNING) + */ + + /* the association procedure will start (wq scheduling)*/ + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATING_RETRY, + + /* the association procedure is sending AUTH request*/ + IEEE80211_ASSOCIATING_AUTHENTICATING, + + /* the association procedure has successfully authentcated + * and is sending association request + */ + IEEE80211_ASSOCIATING_AUTHENTICATED, + + /* the link is ok. the card associated to a BSS or linked + * to a ibss cell or acting as an AP and creating the bss + */ + IEEE80211_LINKED, + + /* same as LINKED, but the driver shall apply RX filter + * rules as we are in NO_LINK mode. As the card is still + * logically linked, but it is doing a syncro site survey + * then it will be back to LINKED state. + */ + IEEE80211_LINKED_SCANNING, + +}; + +#define DEFAULT_MAX_SCAN_AGE (15 * HZ) +#define DEFAULT_FTS 2346 + +#define CFG_IEEE80211_RESERVE_FCS BIT(0) +#define CFG_IEEE80211_COMPUTE_FCS BIT(1) + +#define MAXTID 16 + +#define IEEE_A BIT(0) +#define IEEE_B BIT(1) +#define IEEE_G BIT(2) +#define IEEE_MODE_MASK (IEEE_A | IEEE_B | IEEE_G) + +/* Action category code */ +enum rtw_ieee80211_category { + RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, + RTW_WLAN_CATEGORY_QOS = 1, + RTW_WLAN_CATEGORY_DLS = 2, + RTW_WLAN_CATEGORY_BACK = 3, + RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */ + RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, + RTW_WLAN_CATEGORY_FT = 6, + RTW_WLAN_CATEGORY_HT = 7, + RTW_WLAN_CATEGORY_SA_QUERY = 8, + RTW_WLAN_CATEGORY_TDLS = 12, + RTW_WLAN_CATEGORY_WMM = 17, + RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */ +}; + +/* SPECTRUM_MGMT action code */ +enum rtw_ieee80211_spectrum_mgmt_actioncode { + RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, + RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1, + RTW_WLAN_ACTION_SPCT_TPC_REQ = 2, + RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3, + RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4, + RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, +}; + +enum _PUBLIC_ACTION { + ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */ + ACT_PUBLIC_DSE_ENABLE = 1, + ACT_PUBLIC_DSE_DEENABLE = 2, + ACT_PUBLIC_DSE_REG_LOCATION = 3, + ACT_PUBLIC_EXT_CHL_SWITCH = 4, + ACT_PUBLIC_DSE_MSR_REQ = 5, + ACT_PUBLIC_DSE_MSR_RPRT = 6, + ACT_PUBLIC_MP = 7, /* Measurement Pilot */ + ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, + ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */ + ACT_PUBLIC_GAS_INITIAL_REQ = 10, + ACT_PUBLIC_GAS_INITIAL_RSP = 11, + ACT_PUBLIC_GAS_COMEBACK_REQ = 12, + ACT_PUBLIC_GAS_COMEBACK_RSP = 13, + ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, + ACT_PUBLIC_LOCATION_TRACK = 15, + ACT_PUBLIC_MAX +}; + +/* BACK action code */ +enum rtw_ieee80211_back_actioncode { + RTW_WLAN_ACTION_ADDBA_REQ = 0, + RTW_WLAN_ACTION_ADDBA_RESP = 1, + RTW_WLAN_ACTION_DELBA = 2, +}; + +/* HT features action code */ +enum rtw_ieee80211_ht_actioncode { + RTW_WLAN_ACTION_NOTIFY_CH_WIDTH = 0, + RTW_WLAN_ACTION_SM_PS = 1, + RTW_WLAN_ACTION_PSPM = 2, + RTW_WLAN_ACTION_PCO_PHASE = 3, + RTW_WLAN_ACTION_MIMO_CSI_MX = 4, + RTW_WLAN_ACTION_MIMO_NONCP_BF = 5, + RTW_WLAN_ACTION_MIMP_CP_BF = 6, + RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7, + RTW_WLAN_ACTION_HI_INFO_EXCHG = 8, +}; + +/* BACK (block-ack) parties */ +enum rtw_ieee80211_back_parties { + RTW_WLAN_BACK_RECIPIENT = 0, + RTW_WLAN_BACK_INITIATOR = 1, + RTW_WLAN_BACK_TIMER = 2, +}; + +#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) + * 00:50:F2 + */ +#define WME_OUI_TYPE 2 +#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 +#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 +#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 +#define WME_VERSION 1 + +#define WME_ACTION_CODE_SETUP_REQUEST 0 +#define WME_ACTION_CODE_SETUP_RESPONSE 1 +#define WME_ACTION_CODE_TEARDOWN 2 + +#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0 +#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1 +#define WME_SETUP_RESPONSE_STATUS_REFUSED 3 + +#define WME_TSPEC_DIRECTION_UPLINK 0 +#define WME_TSPEC_DIRECTION_DOWNLINK 1 +#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3 + + +#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ + +#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ + +/** + * enum rtw_ieee80211_channel_flags - channel flags + * + * Channel flags set by the regulatory control code. + * + * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled. + * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted + * on this channel. + * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel. + * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel. + * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel + * is not permitted. + * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel + * is not permitted. + */ +enum rtw_ieee80211_channel_flags { + RTW_IEEE80211_CHAN_DISABLED = BIT(0), + RTW_IEEE80211_CHAN_PASSIVE_SCAN = BIT(1), + RTW_IEEE80211_CHAN_NO_IBSS = BIT(2), + RTW_IEEE80211_CHAN_RADAR = BIT(3), + RTW_IEEE80211_CHAN_NO_HT40PLUS = BIT(4), + RTW_IEEE80211_CHAN_NO_HT40MINUS = BIT(5), +}; + +#define RTW_IEEE80211_CHAN_NO_HT40 \ + (RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS) + +/* Represent channel details, subset of ieee80211_channel */ +struct rtw_ieee80211_channel { + u16 hw_value; + u32 flags; +}; + +#define CHAN_FMT \ + "hw_value:%u, " \ + "flags:0x%08x" \ + +#define CHAN_ARG(channel) \ + (channel)->hw_value \ + , (channel)->flags \ + +/* Parsed Information Elements */ +struct rtw_ieee802_11_elems { + u8 *ssid; + u8 ssid_len; + u8 *supp_rates; + u8 supp_rates_len; + u8 *fh_params; + u8 fh_params_len; + u8 *ds_params; + u8 ds_params_len; + u8 *cf_params; + u8 cf_params_len; + u8 *tim; + u8 tim_len; + u8 *ibss_params; + u8 ibss_params_len; + u8 *challenge; + u8 challenge_len; + u8 *erp_info; + u8 erp_info_len; + u8 *ext_supp_rates; + u8 ext_supp_rates_len; + u8 *wpa_ie; + u8 wpa_ie_len; + u8 *rsn_ie; + u8 rsn_ie_len; + u8 *wme; + u8 wme_len; + u8 *wme_tspec; + u8 wme_tspec_len; + u8 *wps_ie; + u8 wps_ie_len; + u8 *power_cap; + u8 power_cap_len; + u8 *supp_channels; + u8 supp_channels_len; + u8 *mdie; + u8 mdie_len; + u8 *ftie; + u8 ftie_len; + u8 *timeout_int; + u8 timeout_int_len; + u8 *ht_capabilities; + u8 ht_capabilities_len; + u8 *ht_operation; + u8 ht_operation_len; + u8 *vendor_ht_cap; + u8 vendor_ht_cap_len; +}; + +enum parse_res { + ParseOK = 0, + ParseUnknown = 1, + ParseFailed = -1 +}; + +enum parse_res rtw_ieee802_11_parse_elems(u8 *start, uint len, + struct rtw_ieee802_11_elems *elems, + int show_errors); + +u8 *rtw_set_fixed_ie(void *pbuf, unsigned int len, + void *source, unsigned int *frlen); +u8 *rtw_set_ie(u8 *pbuf, int index, uint len, u8 *source, uint *frlen); + +enum secondary_ch_offset { + SCN = 0, /* no secondary channel */ + SCA = 1, /* secondary channel above */ + SCB = 3, /* secondary channel below */ +}; + +u8 *rtw_get_ie(u8 *pbuf, int index, uint *len, int limit); + +void rtw_set_supported_rate(u8 *SupportedRates, uint mode); + +unsigned char *rtw_get_wpa_ie(unsigned char *pie, uint *wpa_ie_len, int limit); +unsigned char *rtw_get_wpa2_ie(unsigned char *pie, uint *rsn_ie_len, int limit); +int rtw_get_wpa_cipher_suite(u8 *s); +int rtw_get_wpa2_cipher_suite(u8 *s); +int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len); +int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, + int *pairwise_cipher, int *is_8021x); +int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, + int *pairwise_cipher, int *is_8021x); + +int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, + u8 *wpa_ie, u16 *wpa_len); + +u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); +u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); +u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id, + u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id, + u8 *buf_content, uint *len_content); + +uint rtw_get_rateset_len(u8 *rateset); + +struct registry_priv; +int rtw_generate_ie(struct registry_priv *pregistrypriv); + + +int rtw_get_bit_value_from_ieee_value(u8 val); + +bool rtw_is_cckrates_included(u8 *rate); + +bool rtw_is_cckratesonly_included(u8 *rate); + +int rtw_check_network_type(unsigned char *rate, int ratelen, int channel); + +void rtw_get_bcn_info(struct wlan_network *pnetwork); + +void rtw_macaddr_cfg(u8 *mac_addr); + +u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, + unsigned char *MCS_rate); + +#endif /* IEEE80211_H */ diff --git a/drivers/staging/rtl8188eu/include/mlme_osdep.h b/drivers/staging/rtl8188eu/include/mlme_osdep.h new file mode 100644 index 0000000..eda16c0 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/mlme_osdep.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __MLME_OSDEP_H_ +#define __MLME_OSDEP_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +void rtw_init_mlme_timer(struct adapter *padapter); +void rtw_os_indicate_disconnect(struct adapter *adapter); +void rtw_os_indicate_connect(struct adapter *adapter); +void rtw_os_indicate_scan_done(struct adapter *padapter, bool aborted); +void rtw_report_sec_ie(struct adapter *adapter, u8 authmode, u8 *sec_ie); + +void rtw_reset_securitypriv(struct adapter *adapter); +void indicate_wx_scan_complete_event(struct adapter *padapter); + +#endif /* _MLME_OSDEP_H_ */ diff --git a/drivers/staging/rtl8188eu/include/mon.h b/drivers/staging/rtl8188eu/include/mon.h new file mode 100644 index 0000000..2977106 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/mon.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RTL8188EU monitor interface + * + * Copyright (C) 2015 Jakub Sitnicki + */ + +/* + * Monitor interface receives all transmitted and received IEEE 802.11 + * frames, both Data and Management, and passes them up to userspace + * preserving the WLAN headers. + */ + +#ifndef _MON_H_ +#define _MON_H_ + +struct net_device; +struct recv_frame; +struct xmit_frame; + +struct net_device *rtl88eu_mon_init(void); +void rtl88eu_mon_deinit(struct net_device *dev); + +void rtl88eu_mon_recv_hook(struct net_device *dev, struct recv_frame *frame); +void rtl88eu_mon_xmit_hook(struct net_device *dev, struct xmit_frame *frame, + uint frag_len); + +#endif /* _MON_H_ */ diff --git a/drivers/staging/rtl8188eu/include/odm.h b/drivers/staging/rtl8188eu/include/odm.h new file mode 100644 index 0000000..947481d --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm.h @@ -0,0 +1,1067 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ + + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +/* Definition */ +/* Define all team support ability. */ + +/* Define for all teams. Please Define the constant in your precomp header. */ + +/* define DM_ODM_SUPPORT_AP 0 */ +/* define DM_ODM_SUPPORT_ADSL 0 */ +/* define DM_ODM_SUPPORT_CE 0 */ +/* define DM_ODM_SUPPORT_MP 1 */ + +/* Define ODM SW team support flag. */ + +/* Antenna Switch Relative Definition. */ + +/* Add new function SwAntDivCheck8192C(). */ +/* This is the main function of Antenna diversity function before link. */ +/* Mainly, it just retains last scan result and scan again. */ +/* After that, it compares the scan result to see which one gets better + * RSSI. It selects antenna with better receiving power and returns better + * scan result. + */ + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + +/* 3 Tx Power Tracking */ +/* 3============================================================ */ +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 + + +/* */ +/* 3 PSD Handler */ +/* 3============================================================ */ + +#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ +#define MODE_40M 0 /* 0:20M, 1:40M */ +#define PSD_TH2 3 +#define PSD_CHM 20 /* Minimum channel number for BT AFH */ +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#define PSD_RESCAN 4 +#define PSD_SCAN_INTERVAL 700 /* ms */ + +/* 8723A High Power IGI Setting */ +#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 +#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 +#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a + +/* LPS define */ +#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ +#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ +#define RSSI_OFFSET_DIG 0x05; + +struct rtw_dig { + u8 Dig_Enable_Flag; + u8 Dig_Ext_Port_Stage; + + int RssiLowThresh; + int RssiHighThresh; + + u32 FALowThresh; + u32 FAHighThresh; + + u8 CurSTAConnectState; + u8 PreSTAConnectState; + u8 CurMultiSTAConnectState; + + u8 PreIGValue; + u8 CurIGValue; + u8 BackupIGValue; + + s8 BackoffVal; + s8 BackoffVal_range_max; + s8 BackoffVal_range_min; + u8 rx_gain_range_max; + u8 rx_gain_range_min; + u8 Rssi_val_min; + + u8 PreCCK_CCAThres; + u8 CurCCK_CCAThres; + u8 PreCCKPDState; + u8 CurCCKPDState; + + u8 LargeFAHit; + u8 ForbiddenIGI; + u32 Recover_cnt; + + u8 DIG_Dynamic_MIN_0; + u8 DIG_Dynamic_MIN_1; + bool bMediaConnect_0; + bool bMediaConnect_1; + + u32 AntDiv_RSSI_max; + u32 RSSI_max; +}; + +struct rtl_ps { + u8 PreCCAState; + u8 CurCCAState; + + u8 PreRFState; + u8 CurRFState; + + int Rssi_val_min; + + u8 initialize; + u32 Reg874, RegC70, Reg85C, RegA74; + +}; + +struct false_alarm_stats { + u32 Cnt_Parity_Fail; + u32 Cnt_Rate_Illegal; + u32 Cnt_Crc8_fail; + u32 Cnt_Mcs_fail; + u32 Cnt_Ofdm_fail; + u32 Cnt_Cck_fail; + u32 Cnt_all; + u32 Cnt_Fast_Fsync; + u32 Cnt_SB_Search_fail; + u32 Cnt_OFDM_CCA; + u32 Cnt_CCK_CCA; + u32 Cnt_CCA_all; + u32 Cnt_BW_USC; /* Gary */ + u32 Cnt_BW_LSC; /* Gary */ +}; + +struct rx_hpc { + u8 RXHP_flag; + u8 PSD_func_trigger; + u8 PSD_bitmap_RXHP[80]; + u8 Pre_IGI; + u8 Cur_IGI; + u8 Pre_pw_th; + u8 Cur_pw_th; + bool First_time_enter; + bool RXHP_enable; + u8 TP_Mode; + struct timer_list PSDTimer; +}; + +#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ +#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM + +/* This indicates two different steps. */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to + * the signal on the air. + */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in + * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to + * switch antenna. + */ + +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +#define TP_MODE 0 +#define RSSI_MODE 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 + +struct sw_ant_switch { + u8 try_flag; + s32 PreRSSI; + u8 CurAntenna; + u8 PreAntenna; + u8 RSSI_Trying; + u8 TestMode; + u8 bTriggerAntennaSwitch; + u8 SelectAntennaMap; + u8 RSSI_target; + + /* Before link Antenna Switch check */ + u8 SWAS_NoLink_State; + u32 SWAS_NoLink_BK_Reg860; + bool ANTA_ON; /* To indicate Ant A is or not */ + bool ANTB_ON; /* To indicate Ant B is on or not */ + + s32 RSSI_sum_A; + s32 RSSI_sum_B; + s32 RSSI_cnt_A; + s32 RSSI_cnt_B; + u64 lastTxOkCnt; + u64 lastRxOkCnt; + u64 TXByteCnt_A; + u64 TXByteCnt_B; + u64 RXByteCnt_A; + u64 RXByteCnt_B; + u8 TrafficLoad; + struct timer_list SwAntennaSwitchTimer; + /* Hybrid Antenna Diversity */ + u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; + u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; + u8 TxAnt[ASSOCIATE_ENTRY_NUM]; + u8 TargetSTA; + u8 antsel; + u8 RxIdleAnt; +}; + +struct edca_turbo { + bool bCurrentTurboEDCA; + bool bIsCurRDLState; + u32 prv_traffic_idx; /* edca turbo */ +}; + +struct odm_rate_adapt { + u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ + u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ + u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ + u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ + u32 LastRATR; /* RATR Register Content */ +}; + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 +#define IQK_BB_REG_NUM 9 +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +#define IQK_Matrix_Settings_NUM 1+24+21 + +#define DM_Type_ByFWi 0 +#define DM_Type_ByDriver 1 + +/* Declare for common info */ + +struct odm_phy_status_info { + u8 RxPWDBAll; + u8 SignalQuality; /* in 0-100 index. */ + u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ + u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ + s8 RxPower; /* in dBm Translate from PWdB */ + s8 RecvSignalPower;/* Real power in dBm for this packet, no + * beautification and aggregation. Keep this raw + * info to be used for the other procedures. + */ + u8 BTRxRSSIPercentage; + u8 SignalStrength; /* in 0-100 index. */ + u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ + u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ +}; + +struct odm_phy_dbg_info { + /* ODM Write,debug info */ + s8 RxSNRdB[MAX_PATH_NUM_92CS]; + u64 NumQryPhyStatus; + u64 NumQryPhyStatusCCK; + u64 NumQryPhyStatusOFDM; + /* Others */ + s32 RxEVM[MAX_PATH_NUM_92CS]; +}; + +struct odm_per_pkt_info { + s8 Rate; + u8 StationID; + bool bPacketMatchBSSID; + bool bPacketToSelf; + bool bPacketBeacon; +}; + +struct odm_mac_status_info { + u8 test; +}; + +enum odm_ability { + /* BB Team */ + ODM_DIG = 0x00000001, + ODM_HIGH_POWER = 0x00000002, + ODM_CCK_CCA_TH = 0x00000004, + ODM_FA_STATISTICS = 0x00000008, + ODM_RAMASK = 0x00000010, + ODM_RSSI_MONITOR = 0x00000020, + ODM_SW_ANTDIV = 0x00000040, + ODM_HW_ANTDIV = 0x00000080, + ODM_BB_PWRSV = 0x00000100, + ODM_2TPATHDIV = 0x00000200, + ODM_1TPATHDIV = 0x00000400, + ODM_PSD2AFH = 0x00000800 +}; + +/* 2011/10/20 MH Define Common info enum for all team. */ + +enum odm_common_info_def { + /* Fixed value: */ + + /* HOOK BEFORE REG INIT----------- */ + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ + ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ + ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ + ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ + ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ + ODM_CMNINFO_EXT_LNA, /* true */ + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + /* HOOK BEFORE REG INIT----------- */ + + /* Dynamic value: */ +/* POINTER REFERENCE----------- */ + ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ + ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ + ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ + ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ + ODM_CMNINFO_BW, /* ODM_BW_E */ + ODM_CMNINFO_CHNL, + + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + ODM_CMNINFO_MP_MODE, +/* POINTER REFERENCE----------- */ + +/* CALL BY VALUE------------- */ + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_DBG_COMP, /* u64 */ + ODM_CMNINFO_DBG_LEVEL, /* u32 */ + ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ + ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ + ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ + ODM_CMNINFO_BT_DISABLED, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_DIG, + ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ + ODM_CMNINFO_BT_DISABLE_EDCA, +/* CALL BY VALUE-------------*/ + + /* Dynamic ptr array hook itms. */ + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_PHY_STATUS, + ODM_CMNINFO_MAC_STATUS, + ODM_CMNINFO_MAX, +}; + +/* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ + +enum odm_ability_def { + /* BB ODM section BIT 0-15 */ + ODM_BB_DIG = BIT(0), + ODM_BB_RA_MASK = BIT(1), + ODM_BB_DYNAMIC_TXPWR = BIT(2), + ODM_BB_FA_CNT = BIT(3), + ODM_BB_RSSI_MONITOR = BIT(4), + ODM_BB_CCK_PD = BIT(5), + ODM_BB_ANT_DIV = BIT(6), + ODM_BB_PWR_SAVE = BIT(7), + ODM_BB_PWR_TRA = BIT(8), + ODM_BB_RATE_ADAPTIVE = BIT(9), + ODM_BB_PATH_DIV = BIT(10), + ODM_BB_PSD = BIT(11), + ODM_BB_RXHP = BIT(12), + + /* MAC DM section BIT 16-23 */ + ODM_MAC_EDCA_TURBO = BIT(16), + ODM_MAC_EARLY_MODE = BIT(17), + + /* RF ODM section BIT 24-31 */ + ODM_RF_TX_PWR_TRACK = BIT(24), + ODM_RF_RX_GAIN_TRACK = BIT(25), + ODM_RF_CALIBRATION = BIT(26), +}; + +#define ODM_RTL8188E BIT(4) + +/* ODM_CMNINFO_CUT_VER */ +enum odm_cut_version { + ODM_CUT_A = 1, + ODM_CUT_B = 2, + ODM_CUT_C = 3, + ODM_CUT_D = 4, + ODM_CUT_E = 5, + ODM_CUT_F = 6, + ODM_CUT_TEST = 7, +}; + +/* ODM_CMNINFO_RF_TYPE */ +/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ +enum odm_rf_path { + ODM_RF_TX_A = BIT(0), + ODM_RF_TX_B = BIT(1), + ODM_RF_TX_C = BIT(2), + ODM_RF_TX_D = BIT(3), + ODM_RF_RX_A = BIT(4), + ODM_RF_RX_B = BIT(5), + ODM_RF_RX_C = BIT(6), + ODM_RF_RX_D = BIT(7), +}; + +enum odm_rf_type { + ODM_1T1R = 0, + ODM_1T2R = 1, + ODM_2T2R = 2, + ODM_2T3R = 3, + ODM_2T4R = 4, + ODM_3T3R = 5, + ODM_3T4R = 6, + ODM_4T4R = 7, +}; + +/* ODM Dynamic common info value definition */ + +enum odm_mac_phy_mode { + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}; + +enum odm_bt_coexist { + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}; + +/* ODM_CMNINFO_OP_MODE */ +enum odm_operation_mode { + ODM_NO_LINK = BIT(0), + ODM_LINK = BIT(1), + ODM_SCAN = BIT(2), + ODM_POWERSAVE = BIT(3), + ODM_AP_MODE = BIT(4), + ODM_CLIENT_MODE = BIT(5), + ODM_AD_HOC = BIT(6), + ODM_WIFI_DIRECT = BIT(7), + ODM_WIFI_DISPLAY = BIT(8), +}; + +/* ODM_CMNINFO_WM_MODE */ +enum odm_wireless_mode { + ODM_WM_UNKNOWN = 0x0, + ODM_WM_B = BIT(0), + ODM_WM_G = BIT(1), + ODM_WM_A = BIT(2), + ODM_WM_N24G = BIT(3), + ODM_WM_N5G = BIT(4), + ODM_WM_AUTO = BIT(5), + ODM_WM_AC = BIT(6), +}; + +/* ODM_CMNINFO_BAND */ +enum odm_band_type { + ODM_BAND_2_4G = BIT(0), + ODM_BAND_5G = BIT(1), +}; + +/* ODM_CMNINFO_SEC_CHNL_OFFSET */ +enum odm_sec_chnl_offset { + ODM_DONT_CARE = 0, + ODM_BELOW = 1, + ODM_ABOVE = 2 +}; + +/* ODM_CMNINFO_SEC_MODE */ +enum odm_security { + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ + ODM_SEC_SMS4 = 7, +}; + +/* ODM_CMNINFO_BW */ +enum odm_bw { + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW10M = 4, +}; + +/* ODM_CMNINFO_BOARD_TYPE */ +enum odm_board_type { + ODM_BOARD_NORMAL = 0, + ODM_BOARD_HIGHPWR = 1, + ODM_BOARD_MINICARD = 2, + ODM_BOARD_SLIM = 3, + ODM_BOARD_COMBO = 4, +}; + +/* ODM_CMNINFO_ONE_PATH_CCA */ +enum odm_cca_path { + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}; + +struct odm_ra_info { + u8 RateID; + u32 RateMask; + u32 RAUseRate; + u8 RateSGI; + u8 RssiStaRA; + u8 PreRssiStaRA; + u8 SGIEnable; + u8 DecisionRate; + u8 PreRate; + u8 HighestRate; + u8 LowestRate; + u32 NscUp; + u32 NscDown; + u16 RTY[5]; + u32 TOTAL; + u16 DROP; + u8 Active; + u16 RptTime; + u8 RAWaitingCounter; + u8 RAPendingCounter; + u8 PTActive; /* on or off */ + u8 PTTryState; /* 0 trying state, 1 for decision state */ + u8 PTStage; /* 0~6 */ + u8 PTStopCount; /* Stop PT counter */ + u8 PTPreRate; /* if rate change do PT */ + u8 PTPreRssi; /* if RSSI change 5% do PT */ + u8 PTModeSS; /* decide whitch rate should do PT */ + u8 RAstage; /* StageRA, decide how many times RA will be done + * between PT + */ + u8 PTSmoothFactor; +}; + +struct ijk_matrix_regs_set { + bool bIQKDone; + s32 Value[1][IQK_Matrix_REG_NUM]; +}; + +struct odm_rf_cal { + /* for tx power tracking */ + u32 RegA24; /* for TempCCK */ + s32 RegE94; + s32 RegE9C; + s32 RegEB4; + s32 RegEBC; + + u8 TXPowercount; + bool bTXPowerTracking; + u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking + * as default + */ + u8 TM_Trigger; + u8 InternalPA5G[2]; /* pathA / pathB */ + + u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, + * and 1 for RFIC1 + */ + u8 ThermalValue; + u8 ThermalValue_LCK; + u8 ThermalValue_IQK; + u8 ThermalValue_DPK; + u8 ThermalValue_AVG[AVG_THERMAL_NUM]; + u8 ThermalValue_AVG_index; + u8 ThermalValue_RxGain; + u8 ThermalValue_Crystal; + u8 ThermalValue_DPKstore; + u8 ThermalValue_DPKtrack; + bool TxPowerTrackingInProgress; + bool bDPKenable; + + bool bReloadtxpowerindex; + u8 bRfPiEnable; + u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ + + u8 bCCKinCH14; + u8 CCK_index; + u8 OFDM_index[2]; + bool bDoneTxpower; + + u8 ThermalValue_HP[HP_THERMAL_NUM]; + u8 ThermalValue_HP_index; + struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + + u8 Delta_IQK; + u8 Delta_LCK; + + /* for IQK */ + u32 RegC04; + u32 Reg874; + u32 RegC08; + u32 RegB68; + u32 RegB6C; + u32 Reg870; + u32 Reg860; + u32 Reg864; + + bool bIQKInitialized; + bool bLCKInProgress; + bool bAntennaDetected; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + + /* for APK */ + u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 bAPKdone; + u8 bAPKThermalMeterIgnore; + u8 bDPdone; + u8 bDPPathAOK; + u8 bDPPathBOK; +}; + +/* ODM Dynamic common info value definition */ + +struct fast_ant_train { + u8 Bssid[6]; + u8 antsel_rx_keep_0; + u8 antsel_rx_keep_1; + u8 antsel_rx_keep_2; + u32 antSumRSSI[7]; + u32 antRSSIcnt[7]; + u32 antAveRSSI[7]; + u8 FAT_State; + u32 TrainIdx; + u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u8 RxIdleAnt; + bool bBecomeLinked; +}; + +enum fat_state { + FAT_NORMAL_STATE = 0, + FAT_TRAINING_STATE = 1, +}; + +enum ant_div_type { + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, +}; + +/* Copy from SD4 defined structure. We use to support PHY DM integration. */ +struct odm_dm_struct { + /* Add for different team use temporarily */ + struct adapter *Adapter; /* For CE/NIC team */ + struct rtl8192cd_priv *priv; /* For AP/ADSL team */ + /* WHen you use above pointers, they must be initialized. */ + bool odm_ready; + + struct rtl8192cd_priv *fake_priv; + u64 DebugComponents; + u32 DebugLevel; + +/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ + bool bCckHighPower; + u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ + u8 ControlChannel; +/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ + +/* 1 COMMON INFORMATION */ + /* Init Value */ +/* HOOK BEFORE REG INIT----------- */ + /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ + u8 SupportPlatform; + /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ + u32 SupportAbility; + /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ + u8 SupportInterface; + /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any + * other type = 1/2/3/... + */ + u32 SupportICType; + /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ + u8 CutVersion; + /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */ + u8 BoardType; + /* with external LNA NO/Yes = 0/1 */ + u8 ExtLNA; + /* with external PA NO/Yes = 0/1 */ + u8 ExtPA; + /* with external TRSW NO/Yes = 0/1 */ + u8 ExtTRSW; + u8 PatchID; /* Customer ID */ + bool bInHctTest; + bool bWIFITest; + + bool bDualMacSmartConcurrent; + u32 BK_SupportAbility; + u8 AntDivType; +/* HOOK BEFORE REG INIT----------- */ + + /* Dynamic Value */ +/* POINTER REFERENCE----------- */ + + u8 u8_temp; + bool bool_temp; + struct adapter *adapter_temp; + + /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ + u8 *pMacPhyMode; + /* TX Unicast byte count */ + u64 *pNumTxBytesUnicast; + /* RX Unicast byte count */ + u64 *pNumRxBytesUnicast; + /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ + u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ + /* Frequence band 2.4G/5G = 0/1 */ + u8 *pBandType; + /* Secondary channel offset don't_care/below/above = 0/1/2 */ + u8 *pSecChOffset; + /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ + u8 *pSecurity; + /* BW info 20M/40M/80M = 0/1/2 */ + u8 *pBandWidth; + /* Central channel location Ch1/Ch2/.... */ + u8 *pChannel; /* central channel number */ + /* Common info for 92D DMSP */ + + bool *pbGetValueFromOtherMac; + struct adapter **pBuddyAdapter; + bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ + /* Common info for Status */ + bool *pbScanInProcess; + bool *pbPowerSaving; + /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ + u8 *pOnePathCCA; + /* pMgntInfo->AntennaTest */ + u8 *pAntennaTest; + bool *pbNet_closed; +/* POINTER REFERENCE----------- */ + /* */ +/* CALL BY VALUE------------- */ + bool bWIFI_Direct; + bool bWIFI_Display; + bool bLinked; + u8 RSSI_Min; + u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ + bool bIsMPChip; + bool bOneEntryOnly; + /* Common info for BTDM */ + bool bBtDisabled; /* BT is disabled */ + bool bBtHsOperation; /* BT HS mode is under progress */ + u8 btHsDigVal; /* use BT rssi to decide the DIG value */ + bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the + * EDCA Turbo + */ + bool bBtBusy; /* BT is busy. */ +/* CALL BY VALUE------------- */ + + /* 2 Define STA info. */ + /* _ODM_STA_INFO */ + /* For MP, we need to reduce one array pointer for default port.??*/ + struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; + + u16 CurrminRptTime; + struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as + * array index. STA MacID=0, + * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} + */ + /* */ + /* 2012/02/14 MH Add to share 88E ra with other SW team. */ + /* We need to colelct all support abilit to a proper area. */ + /* */ + bool RaSupport88E; + + /* Define ........... */ + + /* Latest packet phy info (ODM write) */ + struct odm_phy_dbg_info PhyDbgInfo; + + /* Latest packet phy info (ODM write) */ + struct odm_mac_status_info *pMacInfo; + + /* Different Team independt structure?? */ + + /* ODM Structure */ + struct fast_ant_train DM_FatTable; + struct rtw_dig DM_DigTable; + struct rtl_ps DM_PSTable; + struct rx_hpc DM_RXHP_Table; + struct false_alarm_stats FalseAlmCnt; + struct false_alarm_stats FlaseAlmCntBuddyAdapter; + struct sw_ant_switch DM_SWAT_Table; + bool RSSI_test; + + struct edca_turbo DM_EDCA_Table; + u32 WMMEDCA_BE; + /* Copy from SD4 structure */ + /* */ + /* ================================================== */ + /* */ + + bool *pbDriverStopped; + bool *pbDriverIsGoingToPnpSetPowerSleep; + bool *pinit_adpt_in_progress; + + /* PSD */ + bool bUserAssignLevel; + struct timer_list PSDTimer; + u8 RSSI_BT; /* come from BT */ + bool bPSDinProcess; + bool bDMInitialGainEnable; + + /* for rate adaptive, in fact, 88c/92c fw will handle this */ + u8 bUseRAMask; + + struct odm_rate_adapt RateAdaptive; + + struct odm_rf_cal RFCalibrateInfo; + + /* TX power tracking */ + u8 BbSwingIdxOfdm; + u8 BbSwingIdxOfdmCurrent; + u8 BbSwingIdxOfdmBase; + bool BbSwingFlagOfdm; + u8 BbSwingIdxCck; + u8 BbSwingIdxCckCurrent; + u8 BbSwingIdxCckBase; + bool BbSwingFlagCck; + u8 *mp_mode; + /* ODM system resource. */ + + /* ODM relative time. */ + struct timer_list PathDivSwitchTimer; + /* 2011.09.27 add for Path Diversity */ + struct timer_list CCKPathDiversityTimer; + struct timer_list FastAntTrainingTimer; +}; /* DM_Dynamic_Mechanism_Structure */ + +#define ODM_RF_PATH_MAX 3 + +enum ODM_RF_CONTENT { + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +}; + +/* Status code */ +enum rt_status { + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}; + +/* 3=========================================================== */ +/* 3 DIG */ +/* 3=========================================================== */ + +enum dm_dig_op { + RT_TYPE_THRESH_HIGH = 0, + RT_TYPE_THRESH_LOW = 1, + RT_TYPE_BACKOFF = 2, + RT_TYPE_RX_GAIN_MIN = 3, + RT_TYPE_RX_GAIN_MAX = 4, + RT_TYPE_ENABLE = 5, + RT_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}; + +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ + + +#define DM_false_ALARM_THRESH_LOW 400 +#define DM_false_ALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x4e +#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ + +#define DM_DIG_MAX_AP 0x32 +#define DM_DIG_MIN_AP 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +/* vivi 92c&92d has different definition, 20110504 */ +/* this is for 92c */ +#define DM_DIG_FA_TH0 0x200/* 0x20 */ +#define DM_DIG_FA_TH1 0x300/* 0x100 */ +#define DM_DIG_FA_TH2 0x400/* 0x200 */ +/* this is for 92d */ +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +/* 3=========================================================== */ +/* 3 AGC RX High Power Mode */ +/* 3=========================================================== */ +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +/* 3=========================================================== */ +/* 3 EDCA */ +/* 3=========================================================== */ + +/* 3=========================================================== */ +/* 3 Dynamic Tx Power */ +/* 3=========================================================== */ +/* Dynamic Tx Power Control Threshold */ +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 + +/* 3=========================================================== */ +/* 3 Rate Adaptive */ +/* 3=========================================================== */ +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 + +/* 3=========================================================== */ +/* 3 BB Power Save */ +/* 3=========================================================== */ + + +enum dm_1r_cca { + CCA_1R = 0, + CCA_2R = 1, + CCA_MAX = 2, +}; + +enum dm_rf { + RF_Save = 0, + RF_Normal = 1, + RF_MAX = 2, +}; + +/* 3=========================================================== */ +/* 3 Antenna Diversity */ +/* 3=========================================================== */ +enum dm_swas { + Antenna_A = 1, + Antenna_B = 2, + Antenna_MAX = 3, +}; + +/* Maximal number of antenna detection mechanism needs to perform. */ +#define MAX_ANTENNA_DETECTION_CNT 10 + +/* Extern Global Variables. */ +#define OFDM_TABLE_SIZE_92C 37 +#define OFDM_TABLE_SIZE_92D 43 +#define CCK_TABLE_SIZE 33 + +extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D]; +extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; + +/* check Sta pointer valid or not */ +#define IS_STA_VALID(pSta) (pSta) +/* 20100514 Joseph: Add definition for antenna switching test after link. */ +/* This indicates two different the steps. */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the + * signal on the air. + */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in + * SWAW_STEP_PEAK + */ +/* with original RSSI to determine if it is necessary to switch antenna. */ +#define SWAW_STEP_PEAK 0 +#define SWAW_STEP_DETERMINE 1 + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck +#define dm_RF_Saving ODM_RF_Saving + +void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal); +void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm); +void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm); +void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); +bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, + bool bForceUpdate, u8 *pRATRState); +u32 ConvertTo_dB(u32 Value); +u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, + u32 ra_mask, u8 rssi_level); +void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, u32 Value); +void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value); +void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, void *pValue); +void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, + u16 Index, void *pValue); +void ODM_DMInit(struct odm_dm_struct *pDM_Odm); +void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm); +void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_HWConfig.h b/drivers/staging/rtl8188eu/include/odm_HWConfig.h new file mode 100644 index 0000000..8cef32d --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_HWConfig.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + +/* Definition */ +/* CCK Rates, TxHT = 0 */ +#define DESC92C_RATE1M 0x00 +#define DESC92C_RATE2M 0x01 +#define DESC92C_RATE5_5M 0x02 +#define DESC92C_RATE11M 0x03 + +/* OFDM Rates, TxHT = 0 */ +#define DESC92C_RATE6M 0x04 +#define DESC92C_RATE9M 0x05 +#define DESC92C_RATE12M 0x06 +#define DESC92C_RATE18M 0x07 +#define DESC92C_RATE24M 0x08 +#define DESC92C_RATE36M 0x09 +#define DESC92C_RATE48M 0x0a +#define DESC92C_RATE54M 0x0b + +/* MCS Rates, TxHT = 1 */ +#define DESC92C_RATEMCS0 0x0c +#define DESC92C_RATEMCS1 0x0d +#define DESC92C_RATEMCS2 0x0e +#define DESC92C_RATEMCS3 0x0f +#define DESC92C_RATEMCS4 0x10 +#define DESC92C_RATEMCS5 0x11 +#define DESC92C_RATEMCS6 0x12 +#define DESC92C_RATEMCS7 0x13 +#define DESC92C_RATEMCS8 0x14 +#define DESC92C_RATEMCS9 0x15 +#define DESC92C_RATEMCS10 0x16 +#define DESC92C_RATEMCS11 0x17 +#define DESC92C_RATEMCS12 0x18 +#define DESC92C_RATEMCS13 0x19 +#define DESC92C_RATEMCS14 0x1a +#define DESC92C_RATEMCS15 0x1b +#define DESC92C_RATEMCS15_SG 0x1c +#define DESC92C_RATEMCS32 0x20 + +/* structure and define */ + +struct phy_rx_agc_info { + #ifdef __LITTLE_ENDIAN + u8 gain:7, trsw:1; + #else + u8 trsw:1, gain:7; + #endif +}; + +struct phy_status_rpt { + struct phy_rx_agc_info path_agc[RF_PATH_MAX]; + u8 ch_corr[2]; + u8 cck_sig_qual_ofdm_pwdb_all; + u8 cck_agc_rpt_ofdm_cfosho_a; + u8 cck_rpt_b_ofdm_cfosho_b; + u8 rsvd_1;/* ch_corr_msb; */ + u8 noise_power_db_msb; + u8 path_cfotail[2]; + u8 pcts_mask[2]; + s8 stream_rxevm[2]; + u8 path_rxsnr[3]; + u8 noise_power_db_lsb; + u8 rsvd_2[3]; + u8 stream_csi[2]; + u8 stream_target_csi[2]; + s8 sig_evm; + u8 rsvd_3; + +#ifdef __LITTLE_ENDIAN + u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ + u8 sgi_en:1; + u8 rxsc:2; + u8 idle_long:1; + u8 r_ant_train_en:1; + u8 ant_sel_b:1; + u8 ant_sel:1; +#else /* _BIG_ENDIAN_ */ + u8 ant_sel:1; + u8 ant_sel_b:1; + u8 r_ant_train_en:1; + u8 idle_long:1; + u8 rxsc:2; + u8 sgi_en:1; + u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ +#endif +}; + +void odm_Init_RSSIForDM(struct odm_dm_struct *pDM_Odm); + +void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm, + struct odm_phy_status_info *pPhyInfo, + u8 *pPhyStatus, + struct odm_per_pkt_info *pPktinfo); + +void ODM_MacStatusQuery(struct odm_dm_struct *pDM_Odm, + u8 *pMacStatus, + u8 MacID, + bool bPacketMatchBSSID, + bool bPacketToSelf, + bool bPacketBeacon); + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_debug.h b/drivers/staging/rtl8188eu/include/odm_debug.h new file mode 100644 index 0000000..7ab2483 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_debug.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ + + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + + +/* */ +/* Define the debug levels */ +/* */ +/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */ +/* They can help SW engineer to develop or trace states changed */ +/* and also help HW enginner to trace every operation to and from HW, */ +/* e.g IO, Tx, Rx. */ +/* */ +/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */ +/* which help us to debug SW or HW. */ + +/* Never used in a call to ODM_RT_TRACE()! */ +#define ODM_DBG_OFF 1 + +/* Fatal bug. */ +/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */ +/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */ +#define ODM_DBG_SERIOUS 2 + +/* Abnormal, rare, or unexpected cases. */ +/* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */ +#define ODM_DBG_WARNING 3 + +/* Normal case with useful information about current SW or HW state. */ +/* For example, Tx/Rx descriptor to fill, Tx/Rx descr. completed status, */ +/* SW protocol state change, dynamic mechanism state change and so on. */ +/* */ +#define ODM_DBG_LOUD 4 + +/* Normal case with detail execution flow or information. */ +#define ODM_DBG_TRACE 5 + +/* Define the tracing components */ +/* BB Functions */ +#define ODM_COMP_DIG BIT(0) +#define ODM_COMP_RA_MASK BIT(1) +#define ODM_COMP_DYNAMIC_TXPWR BIT(2) +#define ODM_COMP_FA_CNT BIT(3) +#define ODM_COMP_RSSI_MONITOR BIT(4) +#define ODM_COMP_CCK_PD BIT(5) +#define ODM_COMP_ANT_DIV BIT(6) +#define ODM_COMP_PWR_SAVE BIT(7) +#define ODM_COMP_PWR_TRA BIT(8) +#define ODM_COMP_RATE_ADAPTIVE BIT(9) +#define ODM_COMP_PATH_DIV BIT(10) +#define ODM_COMP_PSD BIT(11) +#define ODM_COMP_DYNAMIC_PRICCA BIT(12) +#define ODM_COMP_RXHP BIT(13) +/* MAC Functions */ +#define ODM_COMP_EDCA_TURBO BIT(16) +#define ODM_COMP_EARLY_MODE BIT(17) +/* RF Functions */ +#define ODM_COMP_TX_PWR_TRACK BIT(24) +#define ODM_COMP_RX_GAIN_TRACK BIT(25) +#define ODM_COMP_CALIBRATION BIT(26) +/* Common Functions */ +#define ODM_COMP_COMMON BIT(30) +#define ODM_COMP_INIT BIT(31) + +/*------------------------Export Marco Definition---------------------------*/ +#define RT_PRINTK(fmt, args...) \ + pr_info("%s(): " fmt, __func__, ## args); + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + if (((comp) & pDM_Odm->DebugComponents) && \ + (level <= pDM_Odm->DebugLevel)) { \ + pr_info("[ODM-8188E] "); \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if (!(expr)) { \ + pr_info("Assertion failed! %s at ......\n", #expr); \ + pr_info(" ......%s,%s,line=%d\n", __FILE__, \ + __func__, __LINE__); \ + RT_PRINTK fmt; \ + ASSERT(false); \ + } + +void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm); + +#endif /* __ODM_DBG_H__ */ diff --git a/drivers/staging/rtl8188eu/include/odm_precomp.h b/drivers/staging/rtl8188eu/include/odm_precomp.h new file mode 100644 index 0000000..658a938 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_precomp.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "odm_types.h" + +#define TEST_FALG___ 1 + +/* 2 Config Flags and Structs - defined by each ODM Type */ + +#include <osdep_service.h> +#include <drv_types.h> +#include <hal_intf.h> +#include <usb_ops_linux.h> + +/* 2 OutSrc Header Files */ + +#include "odm.h" +#include "odm_HWConfig.h" +#include "odm_debug.h" +#include "../../rtlwifi/phydm/phydm_regdefine11n.h" + +#include "hal8188e_rate_adaptive.h" /* for RA,Power training */ +#include "rtl8188e_hal.h" + +#include "odm_reg.h" + +#include "odm_rtl8188e.h" + +void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm); +void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm); +void odm_DIGInit(struct odm_dm_struct *pDM_Odm); +void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm); +void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm); +void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm); +void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm); +void odm_SwAntDivInit_NIC(struct odm_dm_struct *pDM_Odm); +void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm); +void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm); +void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm); +void odm_DIG(struct odm_dm_struct *pDM_Odm); +void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm); +void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm); +void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step); +void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm); +void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm); +void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm); +void odm_1R_CCA(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm); +void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm); +void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm); +void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm); +void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm); +void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm); +void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext); +void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm); +void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm); + +#endif /* __ODM_PRECOMP_H__ */ diff --git a/drivers/staging/rtl8188eu/include/odm_reg.h b/drivers/staging/rtl8188eu/include/odm_reg.h new file mode 100644 index 0000000..b56549b --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_reg.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +/* */ +/* File Name: odm_reg.h */ +/* */ +/* Description: */ +/* */ +/* This file is for general register definition. */ +/* */ +/* */ +/* */ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +/* */ +/* Register Definition */ +/* */ + +/* MAC REG */ +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +/* BB REG */ +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +/* RF REG */ +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 + +/* Ant Detect Reg */ +#define ODM_DPDT 0x300 + +/* PSD Init */ +#define ODM_PSDREG 0x808 + +/* 92D Path Div */ +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +/* */ +/* Bitmap Definition */ +/* */ + +#define BIT_FA_RESET BIT(0) + + + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_rtl8188e.h b/drivers/staging/rtl8188eu/include/odm_rtl8188e.h new file mode 100644 index 0000000..dbf13c4 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_rtl8188e.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __ODM_RTL8188E_H__ +#define __ODM_RTL8188E_H__ + +#define MAIN_ANT 0 +#define AUX_ANT 1 +#define MAIN_ANT_CG_TRX 1 +#define AUX_ANT_CG_TRX 0 +#define MAIN_ANT_CGCS_RX 0 +#define AUX_ANT_CGCS_RX 1 + +void ODM_DIG_LowerBound_88E(struct odm_dm_struct *pDM_Odm); + +void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm); + +void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm); + +void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm, u8 *desc, + u8 mac_id); + +void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant); + +void rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, + u32 mac_id, u8 rx_pwdb_all); + +void odm_FastAntTraining(struct odm_dm_struct *pDM_Odm); + +void odm_FastAntTrainingCallback(struct odm_dm_struct *pDM_Odm); + +void odm_FastAntTrainingWorkItemCallback(struct odm_dm_struct *pDM_Odm); + +bool ODM_DynamicPrimaryCCA_DupRTS(struct odm_dm_struct *pDM_Odm); + +#endif diff --git a/drivers/staging/rtl8188eu/include/odm_types.h b/drivers/staging/rtl8188eu/include/odm_types.h new file mode 100644 index 0000000..7255f7a --- /dev/null +++ b/drivers/staging/rtl8188eu/include/odm_types.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + +#define ODM_CE 0x04 /* BIT2 */ + +enum HAL_STATUS { + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, +}; + +#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) +#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) +#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + +#endif /* __ODM_TYPES_H__ */ diff --git a/drivers/staging/rtl8188eu/include/osdep_intf.h b/drivers/staging/rtl8188eu/include/osdep_intf.h new file mode 100644 index 0000000..07c3276 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/osdep_intf.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ + +#ifndef __OSDEP_INTF_H_ +#define __OSDEP_INTF_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +extern char *rtw_initmac; +extern int rtw_mc2u_disable; + +u8 rtw_init_drv_sw(struct adapter *padapter); +u8 rtw_free_drv_sw(struct adapter *padapter); +u8 rtw_reset_drv_sw(struct adapter *padapter); + +void rtw_stop_drv_threads(struct adapter *padapter); +void rtw_cancel_all_timer(struct adapter *padapter); + +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); + +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); +struct net_device *rtw_init_netdev(struct adapter *padapter); +u16 rtw_recv_select_queue(struct sk_buff *skb); + +int netdev_open(struct net_device *pnetdev); +int ips_netdrv_open(struct adapter *padapter); +void rtw_ips_dev_unload(struct adapter *padapter); +int rtw_ips_pwr_up(struct adapter *padapter); +void rtw_ips_pwr_down(struct adapter *padapter); + +#endif /* _OSDEP_INTF_H_ */ diff --git a/drivers/staging/rtl8188eu/include/osdep_service.h b/drivers/staging/rtl8188eu/include/osdep_service.h new file mode 100644 index 0000000..fbcba79 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/osdep_service.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __OSDEP_SERVICE_H_ +#define __OSDEP_SERVICE_H_ + +#include <basic_types.h> + +#define _FAIL 0 +#define _SUCCESS 1 +#define RTW_RX_HANDLED 2 + +#include <linux/spinlock.h> +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/kref.h> +#include <linux/netdevice.h> +#include <linux/skbuff.h> +#include <linux/circ_buf.h> +#include <linux/uaccess.h> +#include <asm/byteorder.h> +#include <linux/atomic.h> +#include <linux/io.h> +#include <linux/mutex.h> +#include <linux/sem.h> +#include <linux/sched/signal.h> +#include <linux/etherdevice.h> +#include <linux/wireless.h> +#include <net/iw_handler.h> +#include <linux/if_arp.h> +#include <linux/rtnetlink.h> +#include <linux/delay.h> +#include <linux/interrupt.h> /* for struct tasklet_struct */ +#include <linux/ip.h> +#include <linux/kthread.h> + +#include <linux/usb.h> +#include <linux/usb/ch9.h> + +struct __queue { + struct list_head queue; + spinlock_t lock; +}; + +static inline struct list_head *get_list_head(struct __queue *queue) +{ + return &(queue->queue); +} + +static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) +{ + return netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)); +} + +u8 *_rtw_malloc(u32 sz); +#define rtw_malloc(sz) _rtw_malloc((sz)) + +void *rtw_malloc2d(int h, int w, int size); + +void _rtw_init_queue(struct __queue *pqueue); + +struct rtw_netdev_priv_indicator { + void *priv; +}; +struct net_device *rtw_alloc_etherdev_with_old_priv(void *old_priv); + +#define rtw_netdev_priv(netdev) \ + (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv) +void rtw_free_netdev(struct net_device *netdev); + +#define FUNC_NDEV_FMT "%s(%s)" +#define FUNC_NDEV_ARG(ndev) __func__, ndev->name +#define FUNC_ADPT_FMT "%s(%s)" +#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name + +u64 rtw_modular64(u64 x, u64 y); + +/* Macros for handling unaligned memory accesses */ + +#define RTW_GET_BE24(a) ((((u32)(a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ + ((u32)(a)[2])) + +void rtw_buf_free(u8 **buf, u32 *buf_len); +void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); +#endif diff --git a/drivers/staging/rtl8188eu/include/phy.h b/drivers/staging/rtl8188eu/include/phy.h new file mode 100644 index 0000000..e99ac39 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/phy.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <odm.h> + +#define IQK_DELAY_TIME_88E 10 +#define index_mapping_NUM_88E 15 +#define AVG_THERMAL_NUM_88E 4 +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + +bool rtl88eu_phy_mac_config(struct adapter *adapt); +bool rtl88eu_phy_rf_config(struct adapter *adapt); +bool rtl88eu_phy_bb_config(struct adapter *adapt); + +u32 phy_query_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask); +void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data); +u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rf_path, + u32 reg_addr, u32 bit_mask); +void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path, + u32 reg_addr, u32 bit_mask, u32 data); + +void phy_set_tx_power_level(struct adapter *adapt, u8 channel); + +void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, + u8 type, u8 *dir, u32 *out_write); + +void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt); +void rtl88eu_phy_iq_calibrate(struct adapter *adapter, bool recovery); +void rtl88eu_phy_lc_calibrate(struct adapter *adapter); diff --git a/drivers/staging/rtl8188eu/include/pwrseq.h b/drivers/staging/rtl8188eu/include/pwrseq.h new file mode 100644 index 0000000..aa58db5 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/pwrseq.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ + +#ifndef __HAL8188EPWRSEQ_H__ +#define __HAL8188EPWRSEQ_H__ + +#include "pwrseqcmd.h" + +/* + * Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd + * There are 6 HW Power States: + * 0: POFF--Power Off + * 1: PDN--Power Down + * 2: CARDEMU--Card Emulation + * 3: ACT--Active Mode + * 4: LPS--Low Power State + * 5: SUS--Suspend + * + * The transition from different states are defined below + * TRANS_CARDEMU_TO_ACT + * TRANS_ACT_TO_CARDEMU + * TRANS_CARDEMU_TO_SUS + * TRANS_SUS_TO_CARDEMU + * TRANS_CARDEMU_TO_PDN + * TRANS_ACT_TO_LPS + * TRANS_LPS_TO_ACT + * + * TRANS_END + * + * PWR SEQ Version: rtl8188E_PwrSeq_V09.h + */ +#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10 +#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10 +#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10 +#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10 +#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8188E_TRANS_END_STEPS 1 + + +#define RTL8188E_TRANS_CARDEMU_TO_ACT \ + /* format + * { offset, cut_msk, cmd, msk, value + * }, + * comment here + */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ + /* wait till 0x04[17] = 1 power ready*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \ + /* 0x02[1:0] = 0 reset BB*/ \ + {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ + /*0x24[23] = 2b'01 schmit trigger */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ + /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \ + /*0x04[12:11] = 2b'00 disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ + /*0x04[8] = 1 polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \ + /*wait till 0x04[8] = 0*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ + /*LDO normal mode*/ + +#define RTL8188E_TRANS_ACT_TO_CARDEMU \ + /* format + * { offset, cut_msk, cmd, msk, value + * }, + * comments here + */ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \ + /*0x1F[7:0] = 0 turn off RF*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ + /*LDO Sleep mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ + /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \ + /*wait till 0x04[9] = 0 polling until return 0 to disable*/ + +#define RTL8188E_TRANS_CARDEMU_TO_SUS \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ + /* 0x04[12:11] = 2b'01enable WL suspend */ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \ + /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ + {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ + /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ + {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ + /*Set USB suspend enable local register 0xfe10[4]=1 */ + +#define RTL8188E_TRANS_SUS_TO_CARDEMU \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ + /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ + /*0x24[23] = 2b'01 schmit trigger */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ + /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \ + /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\ + {0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ + /*Clear SIC_EN register 0x40[12] = 1'b0 */ \ + {0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ + /*Set USB suspend enable local register 0xfe10[4]=1 */ + +#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \ + /*0x04[12:11] = 2b'01enable WL suspend*/ + +#define RTL8188E_TRANS_CARDEMU_TO_PDN \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ + /* 0x04[16] = 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \ + /* 0x04[15] = 1*/ + +#define RTL8188E_TRANS_PDN_TO_CARDEMU \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \ + /* 0x04[15] = 0*/ + +/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ +#define RTL8188E_TRANS_ACT_TO_LPS \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \ + /*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \ + /*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \ + /*Delay 1us*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \ + /*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \ + /*check if removed later*/\ + {0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \ + /*Respond TxOK to scheduler*/ + + +#define RTL8188E_TRANS_LPS_TO_ACT \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \ + /*USB RPWM*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \ + /*Delay*/ \ + {0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \ + /* 0x08[4] = 0 switch TSF to 40M */ \ + {0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \ + /* Polling 0x109[7]=0 TSF in 40M */ \ + {0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \ + /* 0x29[7:6] = 2b'00 enable BB clock */ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ + /* 0x101[1] = 1 */ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \ + /* 0x100[7:0] = 0xFF enable WMAC TRX */ \ + {0x0002, PWR_CUT_ALL_MSK, \ + PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ + /* 0x02[1:0] = 2b'11 enable BB macro */ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8188E_TRANS_END \ + /* format + * { offset, cut_msk, cmd, msk, + * value }, + * comments here + */ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0}, + + +extern struct wl_pwr_cfg rtl8188E_power_on_flow + [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_radio_off_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_card_disable_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_card_enable_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_suspend_flow[ + RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_resume_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_hwpdn_flow + [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_enter_lps_flow + [RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS]; +extern struct wl_pwr_cfg rtl8188E_leave_lps_flow + [RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS]; + +#endif /* __HAL8188EPWRSEQ_H__ */ diff --git a/drivers/staging/rtl8188eu/include/pwrseqcmd.h b/drivers/staging/rtl8188eu/include/pwrseqcmd.h new file mode 100644 index 0000000..8c73322 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/pwrseqcmd.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __HALPWRSEQCMD_H__ +#define __HALPWRSEQCMD_H__ + +#include <drv_types.h> + +/* The value of cmd: 4 bits */ +#define PWR_CMD_READ 0x00 +#define PWR_CMD_WRITE 0x01 +#define PWR_CMD_POLLING 0x02 +#define PWR_CMD_DELAY 0x03 +#define PWR_CMD_END 0x04 + +/* The value of cut_msk: 8 bits */ +#define PWR_CUT_TESTCHIP_MSK BIT(0) +#define PWR_CUT_A_MSK BIT(1) +#define PWR_CUT_B_MSK BIT(2) +#define PWR_CUT_C_MSK BIT(3) +#define PWR_CUT_D_MSK BIT(4) +#define PWR_CUT_E_MSK BIT(5) +#define PWR_CUT_F_MSK BIT(6) +#define PWR_CUT_G_MSK BIT(7) +#define PWR_CUT_ALL_MSK 0xFF + + +enum pwrseq_cmd_delat_unit { + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +}; + +struct wl_pwr_cfg { + u16 offset; + u8 cut_msk; + u8 cmd:4; + u8 msk; + u8 value; +}; + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + +u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, + struct wl_pwr_cfg pwrcfgCmd[]); + +#endif diff --git a/drivers/staging/rtl8188eu/include/recv_osdep.h b/drivers/staging/rtl8188eu/include/recv_osdep.h new file mode 100644 index 0000000..d234152 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/recv_osdep.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RECV_OSDEP_H_ +#define __RECV_OSDEP_H_ + +#include <osdep_service.h> +#include <drv_types.h> + + +int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter); +void _rtw_free_recv_priv(struct recv_priv *precvpriv); + + +s32 rtw_recv_entry(struct recv_frame *precv_frame); +int rtw_recv_indicatepkt(struct adapter *adapter, + struct recv_frame *recv_frame); + +void rtw_handle_tkip_mic_err(struct adapter *padapter, u8 bgroup); + +int rtw_os_recvbuf_resource_alloc(struct adapter *adapt, struct recv_buf *buf); + +void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); + +#endif /* */ diff --git a/drivers/staging/rtl8188eu/include/rf.h b/drivers/staging/rtl8188eu/include/rf.h new file mode 100644 index 0000000..ed3241c --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rf.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG 0x3F + +void rtl88eu_phy_rf6052_set_bandwidth(struct adapter *adapt, + enum ht_channel_width bandwidth); +void rtl88eu_phy_rf6052_set_cck_txpower(struct adapter *adapt, + u8 *powerlevel); +void rtl88eu_phy_rf6052_set_ofdm_txpower(struct adapter *adapt, + u8 *powerlevel_ofdm, + u8 *powerlevel_bw20, + u8 *powerlevel_bw40, u8 channel); diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_cmd.h b/drivers/staging/rtl8188eu/include/rtl8188e_cmd.h new file mode 100644 index 0000000..e588656 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_cmd.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTL8188E_CMD_H__ +#define __RTL8188E_CMD_H__ + +enum RTL8188E_H2C_CMD_ID { + /* Class Common */ + H2C_COM_RSVD_PAGE = 0x00, + H2C_COM_MEDIA_STATUS_RPT = 0x01, + H2C_COM_SCAN = 0x02, + H2C_COM_KEEP_ALIVE = 0x03, + H2C_COM_DISCNT_DECISION = 0x04, + H2C_COM_INIT_OFFLOAD = 0x06, + H2C_COM_REMOTE_WAKE_CTL = 0x07, + H2C_COM_AP_OFFLOAD = 0x08, + H2C_COM_BCN_RSVD_PAGE = 0x09, + H2C_COM_PROB_RSP_RSVD_PAGE = 0x0A, + + /* Class PS */ + H2C_PS_PWR_MODE = 0x20, + H2C_PS_TUNE_PARA = 0x21, + H2C_PS_TUNE_PARA_2 = 0x22, + H2C_PS_LPS_PARA = 0x23, + H2C_PS_P2P_OFFLOAD = 0x24, + + /* Class DM */ + H2C_DM_MACID_CFG = 0x40, + H2C_DM_TXBF = 0x41, + + /* Class BT */ + H2C_BT_COEX_MASK = 0x60, + H2C_BT_COEX_GPIO_MODE = 0x61, + H2C_BT_DAC_SWING_VAL = 0x62, + H2C_BT_PSD_RST = 0x63, + + /* Class */ + H2C_RESET_TSF = 0xc0, +}; + +enum { + PWRS +}; + +struct setpwrmode_parm { + u8 Mode;/* 0:Active,1:LPS,2:WMMPS */ + u8 SmartPS_RLBM;/* LPS= 0:PS_Poll,1:PS_Poll,2:NullData,WMM= 0:PS_Poll,1:NullData */ + u8 AwakeInterval; /* unit: beacon interval */ + u8 bAllQueueUAPSD; + u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */ +}; + +struct rsvdpage_loc { + u8 LocProbeRsp; + u8 LocPsPoll; + u8 LocNullData; + u8 LocQosNull; + u8 LocBTQosNull; +}; + +/* host message to firmware cmd */ +void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode); +void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus); + +void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt); + +#endif/* __RTL8188E_CMD_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_dm.h b/drivers/staging/rtl8188eu/include/rtl8188e_dm.h new file mode 100644 index 0000000..1920433 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_dm.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTL8188E_DM_H__ +#define __RTL8188E_DM_H__ +enum{ + UP_LINK, + DOWN_LINK, +}; +/* duplicate code,will move to ODM ######### */ +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM 9 +#define HP_THERMAL_NUM 8 +/* duplicate code,will move to ODM ######### */ +struct dm_priv { + u8 DM_Type; + u8 DMFlag; + u8 InitDMFlag; + u32 InitODMFlag; + + /* Upper and Lower Signal threshold for Rate Adaptive*/ + int UndecoratedSmoothedPWDB; + int UndecoratedSmoothedCCK; + int EntryMinUndecoratedSmoothedPWDB; + int EntryMaxUndecoratedSmoothedPWDB; + int MinUndecoratedPWDBForDM; + int LastMinUndecoratedPWDBForDM; + + /* for High Power */ + u8 bDynamicTxPowerEnable; + u8 LastDTPLvl; + u8 DynamicTxHighPowerLvl;/* Tx Power Control for Near/Far Range */ + u8 PowerIndex_backup[6]; +}; + +void rtl8188e_InitHalDm(struct adapter *adapt); + +void AntDivCompare8188E(struct adapter *adapt, struct wlan_bssid_ex *dst, + struct wlan_bssid_ex *src); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_hal.h b/drivers/staging/rtl8188eu/include/rtl8188e_hal.h new file mode 100644 index 0000000..a86b07d --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_hal.h @@ -0,0 +1,372 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTL8188E_HAL_H__ +#define __RTL8188E_HAL_H__ + + +/* include HAL Related header after HAL Related compiling flags */ +#include "rtl8188e_spec.h" +#include "hal8188e_phy_reg.h" +#include "hal8188e_phy_cfg.h" +#include "rtl8188e_dm.h" +#include "rtl8188e_recv.h" +#include "rtl8188e_xmit.h" +#include "rtl8188e_cmd.h" +#include "pwrseq.h" +#include "rtw_efuse.h" +#include "rtw_sreset.h" +#include "odm_precomp.h" + +/* Fw Array */ +#define Rtl8188E_FwImageArray Rtl8188EFwImgArray +#define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength + +#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" +#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" +#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" +#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" +#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" +#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" +#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" +#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" + +/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */ +#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow +#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow +#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow +#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow +#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow +#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow +#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow +#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow +#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow + +#define DRVINFO_SZ 4 /* unit is 8bytes */ +#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0)) + +/* download firmware related data structure */ +#define FW_8188E_SIZE 0x4000 /* 16384,16k */ +#define FW_8188E_START_ADDRESS 0x1000 +#define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */ + +#define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ + +#define IS_FW_HEADER_EXIST(_pFwHdr) \ + ((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 || \ + (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 || \ + (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 || \ + (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0) + +#define DRIVER_EARLY_INT_TIME 0x05 +#define BCN_DMA_ATIME_INT_TIME 0x02 + +enum usb_rx_agg_mode { + USB_RX_AGG_DISABLE, + USB_RX_AGG_DMA, + USB_RX_AGG_USB, + USB_RX_AGG_MIX +}; + +#define MAX_RX_DMA_BUFFER_SIZE_88E \ + 0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8), + * WOLPattern(16*24)) + */ + +#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */ + + +/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */ +#define MAX_TX_QUEUE 9 + +#define TX_SELE_HQ BIT(0) /* High Queue */ +#define TX_SELE_LQ BIT(1) /* Low Queue */ +#define TX_SELE_NQ BIT(2) /* Normal Queue */ + +/* Note: We will divide number of page equally for each queue other + * than public queue! + */ +/* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */ +/* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */ +/* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS + * null-data + */ + +#define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */ + +#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1) + +/* Note: For Normal Chip Setting ,modify later */ +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \ + TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */ +#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \ + (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */ + +/* Chip specific */ +#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) +#define CHIP_BONDING_92C_1T2R 0x1 +#define CHIP_BONDING_88C_USB_MCARD 0x2 +#define CHIP_BONDING_88C_USB_HP 0x1 +#include "HalVerDef.h" +#include "hal_com.h" + +/* Channel Plan */ +enum ChannelPlan { + CHPL_FCC = 0, + CHPL_IC = 1, + CHPL_ETSI = 2, + CHPL_SPA = 3, + CHPL_FRANCE = 4, + CHPL_MKK = 5, + CHPL_MKK1 = 6, + CHPL_ISRAEL = 7, + CHPL_TELEC = 8, + CHPL_GLOBAL = 9, + CHPL_WORLD = 10, +}; + +struct txpowerinfo24g { + u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + /* If only one tx, only BW20 and OFDM are used. */ + s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +}; + +#define EFUSE_REAL_CONTENT_LEN 512 +#define EFUSE_MAX_SECTION 16 +#define EFUSE_IC_ID_OFFSET 506 /* For some inferior IC purpose*/ +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) +/* To prevent out of boundary programming case, */ +/* leave 1byte and program full section */ +/* 9bytes + 1byt + 5bytes and pre 1byte. */ +/* For worst case: */ +/* | 1byte|----8bytes----|1byte|--5bytes--| */ +/* | | Reserved(14bytes) | */ + +/* PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */ +#define EFUSE_OOB_PROTECT_BYTES 15 + +#define HWSET_MAX_SIZE_88E 512 + +#define EFUSE_REAL_CONTENT_LEN_88E 256 +#define EFUSE_MAP_LEN_88E 512 +#define EFUSE_MAP_LEN EFUSE_MAP_LEN_88E +#define EFUSE_MAX_SECTION_88E 64 +#define EFUSE_MAX_WORD_UNIT_88E 4 +#define EFUSE_IC_ID_OFFSET_88E 506 +#define AVAILABLE_EFUSE_ADDR_88E(addr) \ + (addr < EFUSE_REAL_CONTENT_LEN_88E) +/* To prevent out of boundary programming case, leave 1byte and program + * full section + */ +/* 9bytes + 1byt + 5bytes and pre 1byte. */ +/* For worst case: */ +/* | 2byte|----8bytes----|1byte|--7bytes--| 92D */ +/* PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */ +#define EFUSE_OOB_PROTECT_BYTES_88E 18 +#define EFUSE_PROTECT_BYTES_BANK_88E 16 + +/* EFUSE for BT definition */ +#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ +#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ +#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ + +#define EFUSE_PROTECT_BYTES_BANK 16 + +struct hal_data_8188e { + struct HAL_VERSION VersionID; + u16 CustomerID; + u16 FirmwareVersion; + u16 FirmwareVersionRev; + u16 FirmwareSubVersion; + u16 FirmwareSignature; + u8 PGMaxGroup; + /* current WIFI_PHY values */ + u32 ReceiveConfig; + enum wireless_mode CurrentWirelessMode; + enum ht_channel_width CurrentChannelBW; + u8 CurrentChannel; + u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ + + u16 BasicRateSet; + + u8 BoardType; + + /* EEPROM setting. */ + u16 EEPROMVID; + u16 EEPROMPID; + u16 EEPROMSVID; + u16 EEPROMSDID; + u8 EEPROMCustomerID; + u8 EEPROMSubCustomerID; + u8 EEPROMVersion; + u8 EEPROMRegulatory; + + u8 bTXPowerDataReadFromEEPORM; + u8 EEPROMThermalMeter; + u8 bAPKThermalMeterIgnore; + + bool EepromOrEfuse; + /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */ + u8 EfuseMap[2][HWSET_MAX_SIZE_512]; + u8 EfuseUsedPercentage; + struct efuse_hal EfuseHal; + + u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; + /* If only one tx, only BW20 and OFDM are used. */ + s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + + u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT 40MHZ pwr */ + u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT 40MHZ pwr */ + u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* HT 20<->40 Pwr diff */ + u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT<->legacy pwr diff */ + u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For power group */ + u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + + u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */ + /* The current Tx Power Level */ + u8 CurrentCckTxPwrIdx; + u8 CurrentOfdm24GTxPwrIdx; + u8 CurrentBW2024GTxPwrIdx; + u8 CurrentBW4024GTxPwrIdx; + + + /* Read/write are allow for following hardware information variables */ + u8 framesync; + u32 framesyncC34; + u8 framesyncMonitor; + u8 DefaultInitialGain[4]; + u8 pwrGroupCnt; + u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; + u32 CCKTxPowerLevelOriginalOffset; + + u8 CrystalCap; + + u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ + + struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */ + + u32 RfRegChnlVal[2]; + + /* RDG enable */ + bool bRDGEnable; + + /* for host message to fw */ + u8 LastHMEBoxNum; + + u8 RegTxPause; + /* Beacon function related global variable. */ + u32 RegBcnCtrlVal; + u8 RegFwHwTxQCtrl; + u8 RegReg542; + u8 RegCR_1; + + struct dm_priv dmpriv; + struct odm_dm_struct odmpriv; + struct sreset_priv srestpriv; + + u8 CurAntenna; + u8 AntDivCfg; + u8 TRxAntDivType; + + + u8 bDumpRxPkt;/* for debug */ + u8 bDumpTxPkt;/* for debug */ + u8 FwRsvdPageStartOffset; /* Reserve page start offset except + * beacon in TxQ. + */ + + /* 2010/08/09 MH Add CU power down mode. */ + bool pwrdown; + + /* Add for dual MAC 0--Mac0 1--Mac1 */ + u32 interfaceIndex; + + u8 OutEpQueueSel; + u8 OutEpNumber; + + u16 EfuseUsedBytes; + + /* Auto FSM to Turn On, include clock, isolation, power control + * for MAC only + */ + u8 bMacPwrCtrlOn; + + u32 UsbBulkOutSize; + + /* Interrupt relatd register information. */ + u32 IntArray[3];/* HISR0,HISR1,HSISR */ + u32 IntrMask[3]; + u8 C2hArray[16]; + u8 UsbTxAggMode; + u8 UsbTxAggDescNum; + u16 HwRxPageSize; /* Hardware setting */ + u32 MaxUsbRxAggBlock; + + enum usb_rx_agg_mode UsbRxAggMode; + u8 UsbRxAggBlockCount; /* USB Block count. Block size is + * 512-byte in high speed and 64-byte + * in full speed + */ + u8 UsbRxAggBlockTimeout; + u8 UsbRxAggPageCount; /* 8192C DMA page count */ + u8 UsbRxAggPageTimeout; +}; + +/* rtl8188e_hal_init.c */ +void _8051Reset88E(struct adapter *padapter); +void rtl8188e_InitializeFirmwareVars(struct adapter *padapter); + + +s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy); + +/* EFuse */ +void Hal_InitPGData88E(struct adapter *padapter); +void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo); +void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); + +void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, + bool AutoLoadFail); +void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent, + bool AutoloadFail); +void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); + +/* register */ + +void rtl8188e_start_thread(struct adapter *padapter); +void rtl8188e_stop_thread(struct adapter *padapter); + +s32 iol_execute(struct adapter *padapter, u8 control); +void iol_mode_enable(struct adapter *padapter, u8 enable); +s32 rtl8188e_iol_efuse_patch(struct adapter *padapter); +void rtw_cancel_all_timer(struct adapter *padapter); + +#endif /* __RTL8188E_HAL_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_recv.h b/drivers/staging/rtl8188eu/include/rtl8188e_recv.h new file mode 100644 index 0000000..c2c7ef9 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_recv.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTL8188E_RECV_H__ +#define __RTL8188E_RECV_H__ + +#define TX_RPT1_PKT_LEN 8 + +#define RECV_BLK_SZ 512 +#define RECV_BLK_CNT 16 +#define RECV_BLK_TH RECV_BLK_CNT +#define RECV_BULK_IN_ADDR 0x80 +#define RECV_INT_IN_ADDR 0x81 + +#define NR_PREALLOC_RECV_SKB (8) + +#define NR_RECVBUFF (4) + +#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ + +struct phy_stat { + unsigned int phydw0; + unsigned int phydw1; + unsigned int phydw2; + unsigned int phydw3; + unsigned int phydw4; + unsigned int phydw5; + unsigned int phydw6; + unsigned int phydw7; +}; + +/* Rx smooth factor */ +#define Rx_Smooth_Factor (20) + +enum rx_packet_type { + NORMAL_RX,/* Normal rx packet */ + TX_REPORT1,/* CCX */ + TX_REPORT2,/* TX RPT */ + HIS_REPORT,/* USB HISR RPT */ +}; + +#define INTERRUPT_MSG_FORMAT_LEN 60 +void rtl8188eu_recv_tasklet(void *priv); +void rtl8188e_process_phy_info(struct adapter *padapter, + struct recv_frame *prframe); +void update_recvframe_phyinfo_88e(struct recv_frame *fra, struct phy_stat *phy); +void update_recvframe_attrib_88e(struct recv_frame *fra, + struct recv_stat *stat); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_spec.h b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h new file mode 100644 index 0000000..dd943c8 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_spec.h @@ -0,0 +1,1403 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + *******************************************************************************/ +#ifndef __RTL8188E_SPEC_H__ +#define __RTL8188E_SPEC_H__ + +/* 8192C Register offset definition */ + +#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ +#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ + +#define MAC_ADDR_LEN 6 +/* 8188E PKT_BUFF_ACCESS_CTRL value */ +#define TXPKT_BUF_SELECT 0x69 +#define RXPKT_BUF_SELECT 0xA5 +#define DISABLE_TRXPKT_BUF_ACCESS 0x0 + + +/* 0x0000h ~ 0x00FFh System Configuration */ +#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_APS_FSMCO 0x0004 +#define REG_SYS_CLKR 0x0008 +#define REG_9346CR 0x000A +#define REG_EE_VPD 0x000C +#define REG_AFE_MISC 0x0010 +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_RSV_CTRL 0x001C +#define REG_RF_CTRL 0x001F +#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOV12D_CTRL 0x0021 +#define REG_LDOHCI12_CTRL 0x0022 +#define REG_LPLDO_CTRL 0x0023 +#define REG_AFE_XTAL_CTRL 0x0024 +#define REG_AFE_PLL_CTRL 0x0028 +#define REG_APE_PLL_CTRL_EXT 0x002c +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define REG_LEDCFG0 0x004C +#define REG_LEDCFG1 0x004D +#define REG_LEDCFG2 0x004E +#define REG_LEDCFG3 0x004F +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS + * Multi-Function GPIO Pin Control. + */ +#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS + * Multi-Function GPIO Select. + */ +#define REG_BB_PAD_CTRL 0x0064 +#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS + * Multi-Function control source. + */ +#define REG_GPIO_OUTPUT 0x006c +#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ +#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ +#define REG_MCUFWDL 0x0080 +#define REG_WOL_EVENT 0x0081 /* RTL8188E */ +#define REG_MCUTSTCFG 0x0084 +#define REG_HMEBOX_E0 0x0088 +#define REG_HMEBOX_E1 0x008A +#define REG_HMEBOX_E2 0x008C +#define REG_HMEBOX_E3 0x008E +#define REG_HMEBOX_EXT_0 0x01F0 +#define REG_HMEBOX_EXT_1 0x01F4 +#define REG_HMEBOX_EXT_2 0x01F8 +#define REG_HMEBOX_EXT_3 0x01FC +#define REG_HIMR_88E 0x00B0 +#define REG_HISR_88E 0x00B4 +#define REG_HIMRE_88E 0x00B8 +#define REG_HISRE_88E 0x00BC +#define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection + * for RTL8723 + */ +#define REG_BIST_SCAN 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_BIST_ROM_RPT 0x00D8 +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_HPON_FSM 0x00EC +#define REG_SYS_CFG 0x00F0 +#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ +#define REG_TYPE_ID 0x00FC + +#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 + +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ +#define REG_CR 0x0100 +#define REG_PBP 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_TRXDMA_CTRL 0x010C +#define REG_TRXFF_BNDY 0x0114 +#define REG_TRXFF_STATUS 0x0118 +#define REG_RXFF_PTR 0x011C +/* define REG_HIMR 0x0120 */ +/* define REG_HISR 0x0124 */ +#define REG_HIMRE 0x0128 +#define REG_HISRE 0x012C +#define REG_CPWM 0x012F +#define REG_FWIMR 0x0130 +#define REG_FTIMR 0x0138 +#define REG_FWISR 0x0134 +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) +#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL + 2) +#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL + 3) +#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL + 2) +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 + +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 +#define REG_MBIST_DONE 0x0178 +#define REG_MBIST_FAIL 0x017C +#define REG_32K_CTRL 0x0194 /* RTL8188E */ +#define REG_C2HEVT_MSG_NORMAL 0x01A0 +#define REG_C2HEVT_CLEAR 0x01AF +#define REG_MCUTST_1 0x01c0 +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX_0 0x01D0 +#define REG_HMEBOX_1 0x01D4 +#define REG_HMEBOX_2 0x01D8 +#define REG_HMEBOX_3 0x01DC + +#define REG_LLT_INIT 0x01E0 + +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +#define REG_RQPN 0x0200 +#define REG_FIFOPAGE 0x0204 +#define REG_TDECTRL 0x0208 +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 +#define REG_RQPN_NPQ 0x0214 + +/* 0x0280h ~ 0x02FFh RXDMA Configuration */ +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXPKT_NUM 0x0284 +#define REG_RXDMA_STATUS 0x0288 + +/* 0x0300h ~ 0x03FFh PCIe */ +#define REG_PCIE_CTRL_REG 0x0300 +#define REG_INT_MIG 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */ +#define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */ +#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/ +#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */ +#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */ +#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */ +#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */ +#define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */ +#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ +#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ +#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ +#define REG_WATCH_DOG 0x0368 + +/* RTL8723 series ------------------------------ */ +#define REG_PCIE_HISR 0x03A0 + +/* spec version 11 */ +/* 0x0400h ~ 0x047Fh Protocol Configuration */ +#define REG_VOQ_INFORMATION 0x0400 +#define REG_VIQ_INFORMATION 0x0404 +#define REG_BEQ_INFORMATION 0x0408 +#define REG_BKQ_INFORMATION 0x040C +#define REG_MGQ_INFORMATION 0x0410 +#define REG_HGQ_INFORMATION 0x0414 +#define REG_BCNQ_INFORMATION 0x0418 +#define REG_TXPKT_EMPTY 0x041A + +#define REG_CPU_MGQ_INFORMATION 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_HWSEQ_CTRL 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY 0x0425 +#define REG_LIFETIME_EN 0x0426 +#define REG_MULTI_BCNQ_OFFSET 0x0427 +#define REG_SPEC_SIFS 0x0428 +#define REG_RL 0x042A +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1 0x0448 +#define REG_ARFR2 0x044C +#define REG_ARFR3 0x0450 +#define REG_AGGLEN_LMT 0x0458 +#define REG_AMPDU_MIN_SPACE 0x045C +#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D +#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_RD_RESP_PKT_TH 0x0463 +#define REG_INIRTS_RATE_SEL 0x0480 +/* define REG_INIDATA_RATE_SEL 0x0484 */ +#define REG_POWER_STATUS 0x04A4 +#define REG_POWER_STAGE1 0x04B4 +#define REG_POWER_STAGE2 0x04B8 +#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 +#define REG_STBC_SETTING 0x04C4 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_MAX_AGGR_NUM 0x04CA +#define REG_RTS_MAX_AGGR_NUM 0x04CB +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF +#define REG_EARLY_MODE_CONTROL 0x4D0 +#define REG_NQOS_SEQ 0x04DC +#define REG_QOS_SEQ 0x04DE +#define REG_NEED_CPU_HANDLE 0x04E0 +#define REG_PKT_LOSE_RPT 0x04E1 +#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_TX_RPT_CTRL 0x04EC +#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ +#define REG_DUMMY 0x04FC + +/* 0x0500h ~ 0x05FFh EDCA Configuration */ +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CTX 0x0514 +#define REG_SIFS_TRX 0x0516 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +/* Format for offset 540h-542h: + * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting + * beacon content before TBTT. + * + * [7:4]: Reserved. + * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding + * to send the beacon packet. + * + * [23:20]: Reserved + * Description: + * | + * |<--Setup--|--Hold------------>| + * --------------|---------------------- + * | + * TBTT + * Note: We cannot update beacon content to HW or send any AC packets during + * the time between Setup and Hold. + */ +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 +#define REG_BCN_CTRL_1 0x0551 +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_BCN_INTERVAL 0x0554 +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 +#define REG_ATIMWND_1 0x0570 +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACMHWCTRL 0x05C0 + +/* define REG_FW_TSF_SYNC_CNT 0x04A0 */ +#define REG_FW_RESET_TSF_CNT_1 0x05FC +#define REG_FW_RESET_TSF_CNT_0 0x05FD +#define REG_FW_BCN_DIS_CNT 0x05FE + +/* 0x0600h ~ 0x07FFh WMAC Configuration */ +#define REG_APSD_CTRL 0x0600 +#define REG_BWOPMODE 0x0603 +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F + +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG 0x0628 + +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063A + +/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ +/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ +#define REG_R2T_SIFS 0x063C +/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ +#define REG_T2T_SIFS 0x063E +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + +/* RXERR_RPT */ +#define RXERR_TYPE_OFDM_PPDU 0 +#define RXERR_TYPE_OFDM_false_ALARM 1 +#define RXERR_TYPE_OFDM_MPDU_OK 2 +#define RXERR_TYPE_OFDM_MPDU_FAIL 3 +#define RXERR_TYPE_CCK_PPDU 4 +#define RXERR_TYPE_CCK_false_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 6 +#define RXERR_TYPE_CCK_MPDU_FAIL 7 +#define RXERR_TYPE_HT_PPDU 8 +#define RXERR_TYPE_HT_false_ALARM 9 +#define RXERR_TYPE_HT_MPDU_TOTAL 10 +#define RXERR_TYPE_HT_MPDU_OK 11 +#define RXERR_TYPE_HT_MPDU_FAIL 12 +#define RXERR_TYPE_RX_FULL_DROP 15 + +#define RXERR_COUNTER_MASK 0xFFFFF +#define RXERR_RPT_RST BIT(27) +#define _RXERR_RPT_SEL(type) ((type) << 28) + +/* Note: + * The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. + * The default value is always too small, but the WiFi TestPlan test + * by 25,000 microseconds of NAV through sending CTS in the air. + * We must update this value greater than 25,000 microseconds to pass + * the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and + * the offset should be 0x0652. + */ +#define REG_NAV_UPPER 0x0652 /* unit of 128 */ + +/* WMA, BA, CCX */ +/* define REG_NAV_CTRL 0x0650 */ +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 +#define REG_FWDLY 0x0661 +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 + +/* Security */ +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +/* Power */ +#define REG_WOW_CTRL 0x0690 +#define REG_PS_RX_INFO 0x0692 +#define REG_UAPSD_TID 0x0693 +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_NUM_88E 0x698 +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP2 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 +#define REG_BT_COEX_TABLE 0x06C0 + +/* Hardware Port 2 */ +#define REG_MACID1 0x0700 +#define REG_BSSID1 0x0708 + +/* 0xFE00h ~ 0xFE55h USB Configuration */ +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +/* For normal chip */ +#define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ +#define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ +#define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ +#define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ + +/* TODO: use these definition when using REG_xxx naming rule. */ +/* NOTE: DO NOT Remove these definition. Use later. */ + +#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ +#define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ +#define MSR (REG_CR + 2) /* Media Status reg */ +#define ISR REG_HISR_88E +/* Timing Sync Function Timer Register. */ +#define TSFR REG_TSFTR + +#define PBP REG_PBP + +/* Redifine MACID register, to compatible prior ICs. */ +/* MAC ID Register, Offset 0x0050-0x0053 */ +#define IDR0 REG_MACID +/* MAC ID Register, Offset 0x0054-0x0055 */ +#define IDR4 (REG_MACID + 4) + +/* 9. Security Control Registers (Offset: ) */ +/* IN 8190 Data Sheet is called CAMcmd */ +#define RWCAM REG_CAMCMD +/* Software write CAM input content */ +#define WCAMI REG_CAMWRITE +/* Software read/write CAM config */ +#define RCAMO REG_CAMREAD +#define CAMDBG REG_CAMDBG +/* Security Configuration Register */ +#define SECR REG_SECCFG + +/* Unused register */ +#define UnusedRegister 0x1BF +#define DCAM UnusedRegister +#define PSR UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister + +/* Min Spacing related settings. */ +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A + +/* EEPROM enable when set 1 */ +#define CmdEEPROM_En BIT(5) +/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ +#define CmdEERPOMSEL BIT(4) +#define Cmd9346CR_9356SEL BIT(4) + +/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ +#define GPIOSEL_GPIO 0 +#define GPIOSEL_ENBT BIT(5) + +/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ +/* GPIO pins input value */ +#define GPIO_IN REG_GPIO_PIN_CTRL +/* GPIO pins output value */ +#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1) +/* GPIO pins output enable when a bit is set to "1"; otherwise, + * input is configured. + */ +#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2) +#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3) + +/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ +#define HSIMR_GPIO12_0_INT_EN BIT(0) +#define HSIMR_SPS_OCP_INT_EN BIT(5) +#define HSIMR_RON_INT_EN BIT(6) +#define HSIMR_PDN_INT_EN BIT(7) +#define HSIMR_GPIO9_INT_EN BIT(25) + +/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ +#define HSISR_GPIO12_0_INT BIT(0) +#define HSISR_SPS_OCP_INT BIT(5) +#define HSISR_RON_INT_EN BIT(6) +#define HSISR_PDNINT BIT(7) +#define HSISR_GPIO9_INT BIT(25) + +/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ +/* + * Network Type + * 00: No link + * 01: Link in ad hoc network + * 10: Link in infrastructure network + * 11: AP mode + * Default: 00b. + */ +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + +/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */ +#define USB_INTR_CONTENT_C2H_OFFSET 0 +#define USB_INTR_CONTENT_CPWM1_OFFSET 16 +#define USB_INTR_CONTENT_CPWM2_OFFSET 20 +#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISRE_OFFSET 52 + +/* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ +/* IOL config for REG_FDHM0(Reg0x88) */ +#define CMD_INIT_LLT BIT(0) +#define CMD_READ_EFUSE_MAP BIT(1) +#define CMD_EFUSE_PATCH BIT(2) +#define CMD_IOCONFIG BIT(3) +#define CMD_INIT_LLT_ERR BIT(4) +#define CMD_READ_EFUSE_MAP_ERR BIT(5) +#define CMD_EFUSE_PATCH_ERR BIT(6) +#define CMD_IOCONFIG_ERR BIT(7) + +/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ +/* 8192C Response Rate Set Register (offset 0x181, 24bits) */ +#define RRSR_1M BIT(0) +#define RRSR_2M BIT(1) +#define RRSR_5_5M BIT(2) +#define RRSR_11M BIT(3) +#define RRSR_6M BIT(4) +#define RRSR_9M BIT(5) +#define RRSR_12M BIT(6) +#define RRSR_18M BIT(7) +#define RRSR_24M BIT(8) +#define RRSR_36M BIT(9) +#define RRSR_48M BIT(10) +#define RRSR_54M BIT(11) +#define RRSR_MCS0 BIT(12) +#define RRSR_MCS1 BIT(13) +#define RRSR_MCS2 BIT(14) +#define RRSR_MCS3 BIT(15) +#define RRSR_MCS4 BIT(16) +#define RRSR_MCS5 BIT(17) +#define RRSR_MCS6 BIT(18) +#define RRSR_MCS7 BIT(19) + +/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ +/* WOL bit information */ +#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) +#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) + +/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ +#define BW_OPMODE_20MHZ BIT(2) +#define BW_OPMODE_5G BIT(1) + +/* 8192C CAM Config Setting (offset 0x250, 1 byte) */ +#define CAM_VALID BIT(15) +#define CAM_NOTVALID 0x0000 +#define CAM_USEDK BIT(5) + +#define CAM_CONTENT_COUNT 8 + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 + +#define TOTAL_CAM_ENTRY 32 +#define HALF_CAM_ENTRY 16 + +#define CAM_CONFIG_USEDK true +#define CAM_CONFIG_NO_USEDK false + +#define CAM_WRITE BIT(16) +#define CAM_READ 0x00000000 +#define CAM_POLLINIG BIT(31) + +#define SCR_UseDK 0x01 +#define SCR_TxSecEnable 0x02 +#define SCR_RxSecEnable 0x04 + +/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ +#define WOW_PMEN BIT(0) /* Power management Enable. */ +#define WOW_WOMEN BIT(1) /* WoW function on or off. */ +#define WOW_MAGIC BIT(2) /* Magic packet */ +#define WOW_UWF BIT(3) /* Unicast Wakeup frame. */ + +/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ +/* 8188 IMR/ISR bits */ +#define IMR_DISABLED_88E 0x0 +/* IMR DW0(0x0060-0063) Bit 0-31 */ +#define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */ +#define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */ +#define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ +#define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_88E BIT(0) /* Receive DMA OK */ + +/* IMR DW1(0x00B4-00B7) Bit 0-31 */ +#define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDERR7_88E BIT(20) /* Beacon DMA Error Int 7 */ +#define IMR_BCNDERR6_88E BIT(19) /* Beacon DMA Error Int 6 */ +#define IMR_BCNDERR5_88E BIT(18) /* Beacon DMA Error Int 5 */ +#define IMR_BCNDERR4_88E BIT(17) /* Beacon DMA Error Int 4 */ +#define IMR_BCNDERR3_88E BIT(16) /* Beacon DMA Error Int 3 */ +#define IMR_BCNDERR2_88E BIT(15) /* Beacon DMA Error Int 2 */ +#define IMR_BCNDERR1_88E BIT(14) /* Beacon DMA Error Int 1 */ +#define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Ext for Win7 */ +#define IMR_TXERR_88E BIT(11) /* Tx Err Flag Int Status, write 1 clear. */ +#define IMR_RXERR_88E BIT(10) /* Rx Err Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */ + +#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ + +/* 8192C EFUSE */ +#define HWSET_MAX_SIZE 256 +#define HWSET_MAX_SIZE_88E 512 + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* + * Based on Datasheet V33---090401 + * Register Summary + * Current IOREG MAP + * 0x0000h ~ 0x00FFh System Configuration (256 Bytes) + * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) + * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) + * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) + * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) + * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) + * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) + * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) + * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) + */ +/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ +/* Note: + * The bits of stopping AC(VO/VI/BE/BK) queue in datasheet + * RTL8192S/RTL8192C are wrong, + * the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, + * and BK - Bit3. + * 8723 and 88E may be not correct either in the earlier version. + */ +#define StopBecon BIT(6) +#define StopHigh BIT(5) +#define StopMgt BIT(4) +#define StopBK BIT(3) +#define StopBE BIT(2) +#define StopVI BIT(1) +#define StopVO BIT(0) + +/* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */ +#define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */ +#define RCR_APP_MIC BIT(30) +#define RCR_APP_PHYSTS BIT(28) +#define RCR_APP_ICV BIT(29) +#define RCR_APP_PHYST_RXFF BIT(28) +#define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */ +#define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */ +#define RCR_LSIGEN BIT(23) +#define RCR_MFBEN BIT(22) +#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ +#define RCR_AMF BIT(13) /* Accept management type frame */ +#define RCR_ACF BIT(12) /* Accept control type frame */ +#define RCR_ADF BIT(11) /* Accept data type frame */ +#define RCR_AICV BIT(9) /* Accept ICV error packet */ +#define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */ +#define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet + * (Rx beacon, probe rsp) + */ +#define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match (Data)*/ +#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */ +#define RCR_APWRMGT BIT(5) /* Accept power management pkt*/ +#define RCR_ADD3 BIT(4) /* Accept address 3 match pkt */ +#define RCR_AB BIT(3) /* Accept broadcast packet */ +#define RCR_AM BIT(2) /* Accept multicast packet */ +#define RCR_APM BIT(1) /* Accept physical match pkt */ +#define RCR_AAP BIT(0) /* Accept all unicast packet */ +#define RCR_MXDMA_OFFSET 8 +#define RCR_FIFO_OFFSET 13 + +/* 0xFE00h ~ 0xFE55h USB Configuration */ +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 +/* 8192C Register Bit and Content definition */ +/* 0x0000h ~ 0x00FFh System Configuration */ + +/* 2 SYS_ISO_CTRL */ +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + +/* 2 SYS_FUNC_EN */ +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +/* 2 APS_FSMCO */ +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +/* 2 SYS_CLKR */ +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + +/* 2 9346CR */ + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + +/* 2 SPS0_CTRL */ + +/* 2 SPS_OCP_CFG */ + +/* 2 RF_CTRL */ +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +/* 2 LDOV12D_CTRL */ +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + +/* 2EFUSE_CTRL */ +#define ALD_EN BIT(18) +#define EF_PD BIT(19) +#define EF_FLAG BIT(31) + +/* 2 EFUSE_TEST (For RTL8723 partially) */ +#define EF_TRPT BIT(7) +/* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ +#define EF_CELL_SEL (BIT(8) | BIT(9)) +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + +#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ +#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ + +/* 2 8051FWDL */ +/* 2 MCUFWDL */ +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + +/* 2 REG_SYS_CFG */ +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define SW_OFFLOAD_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) /* RTL ID */ +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ +#define CHIP_VER_RTL_SHIFT 12 + +/* 2REG_GPIO_OUTSTS (For RTL8723 only) */ +#define EFS_HCI_SEL (BIT(0) | BIT(1)) +#define PAD_HCI_SEL (BIT(2) | BIT(3)) +#define HCI_SEL (BIT(4) | BIT(5)) +#define PKG_SEL_HCI BIT(6) +#define FEN_GPS BIT(7) +#define FEN_BT BIT(8) +#define FEN_WL BIT(9) +#define FEN_PCI BIT(10) +#define FEN_USB BIT(11) +#define BTRF_HWPDN_N BIT(12) +#define WLRF_HWPDN_N BIT(13) +#define PDN_BT_N BIT(14) +#define PDN_GPS_N BIT(15) +#define BT_CTL_HWPDN BIT(16) +#define GPS_CTL_HWPDN BIT(17) +#define PPHY_SUSB BIT(20) +#define UPHY_SUSB BIT(21) +#define PCI_SUSEN BIT(22) +#define USB_SUSEN BIT(23) +#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) + +/* 2SYS_CFG */ +#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ + +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ + +/* 2 Function Enable Registers */ +/* 2 CR */ + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ + +/* Network type */ +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + +/* 2 PBP - Page Size Register */ +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + +/* 2 TX/RXDMA */ +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +/* For normal driver, 0x10C */ +#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8) +#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6) +#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + +/* 2 TRXFF_BNDY */ + +/* 2 LLT_INIT */ +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +/* 2RQPN */ +#define _HPQ(x) ((x) & 0xFF) +#define _LPQ(x) (((x) & 0xFF) << 8) +#define _PUBQ(x) (((x) & 0xFF) << 16) +/* NOTE: in RQPN_NPQ register */ +#define _NPQ(x) ((x) & 0xFF) + +#define HPQ_PUBLIC_DIS BIT(24) +#define LPQ_PUBLIC_DIS BIT(25) +#define LD_RQPN BIT(31) + +/* 2TDECTRL */ +#define BCN_VALID BIT(16) +#define BCN_HEAD(x) (((x) & 0xFF) << 8) +#define BCN_HEAD_MASK 0xFF00 + +/* 2 TDECTL */ +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + +/* 2 TXDMA_OFFSET_CHK */ +#define DROP_DATA_EN BIT(9) + +/* 0x0280h ~ 0x028Bh RX DMA Configuration */ + +/* REG_RXDMA_CONTROL, 0x0286h */ + +/* 2 REG_RXPKT_NUM, 0x0284 */ +#define RXPKT_RELEASE_POLL BIT(16) +#define RXDMA_IDLE BIT(17) +#define RW_RELEASE_EN BIT(18) + +/* 0x0400h ~ 0x047Fh Protocol Configuration */ +/* 2 FWHW_TXQ_CTRL */ +#define EN_AMPDU_RTY_NEW BIT(7) + +/* 2 SPEC SIFS */ +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +/* 2 RL */ +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +/* 0x0500h ~ 0x05FFh EDCA Configuration */ + +/* 2 EDCA setting */ +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) + +/* 2 BCN_CTRL */ +#define EN_MBSSID BIT(1) +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) +#define DIS_TSF_UPDATE BIT(3) + +/* The same function but different bit field. */ +#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) +#define DIS_TSF_UDT0_TEST_CHIP BIT(5) +#define STOP_BCNQ BIT(6) + +/* 2 ACMHWCTRL */ +#define AcmHw_HwEn BIT(0) +#define AcmHw_BeqEn BIT(1) +#define AcmHw_ViqEn BIT(2) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) +#define AcmHw_ViqStatus BIT(5) +#define AcmHw_VoqStatus BIT(6) + +/* 0x0600h ~ 0x07FFh WMAC Configuration */ +/* 2APSD_CTRL */ +#define APSDOFF BIT(6) +#define APSDOFF_STATUS BIT(7) + +#define RATE_BITMAP_ALL 0xFFFFF + +/* Only use CCK 1M rate for ACK */ +#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 + +/* 2 TCR */ +#define TSFRST BIT(0) +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) + +/* 2 RCR */ +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +#define APP_FCS BIT(31) + +/* 2 SECCFG */ +#define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ +#define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ +#define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ +#define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ +#define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ +#define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ +#define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */ +#define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */ + +/* RTL8188E SDIO Configuration */ + +/* I/O bus domain address mapping */ +#define SDIO_LOCAL_BASE 0x10250000 +#define WLAN_IOREG_BASE 0x10260000 +#define FIRMWARE_FIFO_BASE 0x10270000 +#define TX_HIQ_BASE 0x10310000 +#define TX_MIQ_BASE 0x10320000 +#define TX_LOQ_BASE 0x10330000 +#define RX_RX0FF_BASE 0x10340000 + +/* SDIO host local register space mapping. */ +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ +#define WLAN_RX0FF_MSK 0x0003 + +/* Without ref to the SDIO Device ID */ +#define SDIO_WITHOUT_REF_DEVICE_ID 0 +#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ +#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ +#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ +#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ +#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ +#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ + +/* SDIO Tx Free Page Index */ +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ +#define SDIO_MAX_RX_QUEUE 1 + +/* SDIO Tx Control */ +#define SDIO_REG_TX_CTRL 0x0000 +/* SDIO Host Interrupt Mask */ +#define SDIO_REG_HIMR 0x0014 +/* SDIO Host Interrupt Service Routine */ +#define SDIO_REG_HISR 0x0018 +/* HCI Current Power Mode */ +#define SDIO_REG_HCPWM 0x0019 +/* RXDMA Request Length */ +#define SDIO_REG_RX0_REQ_LEN 0x001C +/* Free Tx Buffer Page */ +#define SDIO_REG_FREE_TXPG 0x0020 +/* HCI Current Power Mode 1 */ +#define SDIO_REG_HCPWM1 0x0024 +/* HCI Current Power Mode 2 */ +#define SDIO_REG_HCPWM2 0x0026 +/* HTSF Informaion */ +#define SDIO_REG_HTSFR_INFO 0x0030 +/* HCI Request Power Mode 1 */ +#define SDIO_REG_HRPWM1 0x0080 +/* HCI Request Power Mode 2 */ +#define SDIO_REG_HRPWM2 0x0082 +/* HCI Power Save Clock */ +#define SDIO_REG_HPS_CLKR 0x0084 +/* SDIO HCI Suspend Control */ +#define SDIO_REG_HSUS_CTRL 0x0086 +/* SDIO Host Extension Interrupt Mask Always */ +#define SDIO_REG_HIMR_ON 0x0090 +/* SDIO Host Extension Interrupt Status Always */ +#define SDIO_REG_HISR_ON 0x0091 + +#define SDIO_HIMR_DISABLED 0 + +/* RTL8188E SDIO Host Interrupt Mask Register */ +#define SDIO_HIMR_RX_REQUEST_MSK BIT(0) +#define SDIO_HIMR_AVAL_MSK BIT(1) +#define SDIO_HIMR_TXERR_MSK BIT(2) +#define SDIO_HIMR_RXERR_MSK BIT(3) +#define SDIO_HIMR_TXFOVW_MSK BIT(4) +#define SDIO_HIMR_RXFOVW_MSK BIT(5) +#define SDIO_HIMR_TXBCNOK_MSK BIT(6) +#define SDIO_HIMR_TXBCNERR_MSK BIT(7) +#define SDIO_HIMR_BCNERLY_INT_MSK BIT(16) +#define SDIO_HIMR_C2HCMD_MSK BIT(17) +#define SDIO_HIMR_CPWM1_MSK BIT(18) +#define SDIO_HIMR_CPWM2_MSK BIT(19) +#define SDIO_HIMR_HSISR_IND_MSK BIT(20) +#define SDIO_HIMR_GTINT3_IND_MSK BIT(21) +#define SDIO_HIMR_GTINT4_IND_MSK BIT(22) +#define SDIO_HIMR_PSTIMEOUT_MSK BIT(23) +#define SDIO_HIMR_OCPINT_MSK BIT(24) +#define SDIO_HIMR_ATIMEND_MSK BIT(25) +#define SDIO_HIMR_ATIMEND_E_MSK BIT(26) +#define SDIO_HIMR_CTWEND_MSK BIT(27) + +/* RTL8188E SDIO Specific */ +#define SDIO_HIMR_MCU_ERR_MSK BIT(28) +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29) + +/* SDIO Host Interrupt Service Routine */ +#define SDIO_HISR_RX_REQUEST BIT(0) +#define SDIO_HISR_AVAL BIT(1) +#define SDIO_HISR_TXERR BIT(2) +#define SDIO_HISR_RXERR BIT(3) +#define SDIO_HISR_TXFOVW BIT(4) +#define SDIO_HISR_RXFOVW BIT(5) +#define SDIO_HISR_TXBCNOK BIT(6) +#define SDIO_HISR_TXBCNERR BIT(7) +#define SDIO_HISR_BCNERLY_INT BIT(16) +#define SDIO_HISR_C2HCMD BIT(17) +#define SDIO_HISR_CPWM1 BIT(18) +#define SDIO_HISR_CPWM2 BIT(19) +#define SDIO_HISR_HSISR_IND BIT(20) +#define SDIO_HISR_GTINT3_IND BIT(21) +#define SDIO_HISR_GTINT4_IND BIT(22) +#define SDIO_HISR_PSTIME BIT(23) +#define SDIO_HISR_OCPINT BIT(24) +#define SDIO_HISR_ATIMEND BIT(25) +#define SDIO_HISR_ATIMEND_E BIT(26) +#define SDIO_HISR_CTWEND BIT(27) + +/* RTL8188E SDIO Specific */ +#define SDIO_HISR_MCU_ERR BIT(28) +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29) + +#define MASK_SDIO_HISR_CLEAR \ + (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\ + SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\ + SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\ + SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\ + SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT) + +/* SDIO HCI Suspend Control Register */ +#define HCI_RESUME_PWR_RDY BIT(1) +#define HCI_SUS_CTRL BIT(0) + +/* SDIO Tx FIFO related */ +/* The number of Tx FIFO free page */ +#define SDIO_TX_FREE_PG_QUEUE 4 +#define SDIO_TX_FIFO_PAGE_SZ 128 + +/* 0xFE00h ~ 0xFE55h USB Configuration */ + +/* 2 USB Information (0xFE17) */ +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +/* 2 Special Option */ +#define USB_AGG_EN BIT(3) + +/* 0; Use interrupt endpoint to upload interrupt pkt */ +/* 1; Use bulk endpoint to upload interrupt pkt, */ +#define INT_BULK_SEL BIT(4) + +/* 2REG_C2HEVT_CLEAR */ +/* Set by driver and notify FW that the driver has read + * the C2H command message + */ +#define C2H_EVT_HOST_CLOSE 0x00 +/* Set by FW indicating that FW had set the C2H command + * message and it's not yet read by driver. + */ +#define C2H_EVT_FW_CLOSE 0xFF + +/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ +/* Enable GPIO[9] as WiFi HW PDn source */ +#define WL_HWPDN_EN BIT(0) +/* WiFi HW PDn polarity control */ +#define WL_HWPDN_SL BIT(1) +/* WiFi function enable */ +#define WL_FUNC_EN BIT(2) +/* Enable GPIO[9] as WiFi RF HW PDn source */ +#define WL_HWROF_EN BIT(3) +/* Enable GPIO[11] as BT HW PDn source */ +#define BT_HWPDN_EN BIT(16) +/* BT HW PDn polarity control */ +#define BT_HWPDN_SL BIT(17) +/* BT function enable */ +#define BT_FUNC_EN BIT(18) +/* Enable GPIO[11] as BT/GPS RF HW PDn source */ +#define BT_HWROF_EN BIT(19) +/* Enable GPIO[10] as GPS HW PDn source */ +#define GPS_HWPDN_EN BIT(20) +/* GPS HW PDn polarity control */ +#define GPS_HWPDN_SL BIT(21) +/* GPS function enable */ +#define GPS_FUNC_EN BIT(22) + +/* 3 REG_LIFECTRL_CTRL */ +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */ + +/* General definitions */ +#define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */ + +#define POLLING_LLT_THRESHOLD 20 +#define POLLING_READY_TIMEOUT_COUNT 1000 +/* GPIO BIT */ +#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) + +/* 8192C EEPROM/EFUSE share register definition. */ + +/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */ +#define EEPROM_TX_PWR_INX_88E 0x10 + +#define EEPROM_ChannelPlan_88E 0xB8 +#define EEPROM_XTAL_88E 0xB9 +#define EEPROM_THERMAL_METER_88E 0xBA +#define EEPROM_IQK_LCK_88E 0xBB + +#define EEPROM_RF_BOARD_OPTION_88E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 +#define EEPROM_RF_BT_SETTING_88E 0xC3 +#define EEPROM_VERSION_88E 0xC4 +#define EEPROM_CUSTOMERID_88E 0xC5 +#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 + +/* RTL88EE */ +#define EEPROM_MAC_ADDR_88EE 0xD0 +#define EEPROM_VID_88EE 0xD6 +#define EEPROM_DID_88EE 0xD8 +#define EEPROM_SVID_88EE 0xDA +#define EEPROM_SMID_88EE 0xDC + +/* RTL88EU */ +#define EEPROM_MAC_ADDR_88EU 0xD7 +#define EEPROM_VID_88EU 0xD0 +#define EEPROM_PID_88EU 0xD2 +#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 + +/* RTL88ES */ +#define EEPROM_MAC_ADDR_88ES 0x11A + +/* EEPROM/Efuse Value Type */ +#define EETYPE_TX_PWR 0x0 + +/* Default Value for EEPROM or EFUSE!!! */ +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_TxPowerDiff 0x0 +#define EEPROM_Default_CrystalCap 0x5 +/* Default: 2X2, RTL8192CE(QFPN68) */ +#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_Default_HT2T_TxPwr 0x10 + +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_ThermalMeter 0x12 + +#define EEPROM_Default_AntTxPowerDiff 0x0 +#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 +#define EEPROM_Default_TxPowerLevel 0x2A + +#define EEPROM_Default_HT40_2SDiff 0x0 +/* HT20<->40 default Tx Power Index Difference */ +#define EEPROM_Default_HT20_Diff 2 +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_HT40_PwrMaxOffset 0 +#define EEPROM_Default_HT20_PwrMaxOffset 0 + +#define EEPROM_Default_CrystalCap_88E 0x20 +#define EEPROM_Default_ThermalMeter_88E 0x18 + +/* New EFUSE default value */ +#define EEPROM_DEFAULT_24G_INDEX 0x2D +#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 +#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_5G_INDEX 0X2A +#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 +#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_DIFF 0XFE +#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F +#define EEPROM_DEFAULT_BOARD_OPTION 0x00 +#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 +#define EEPROM_DEFAULT_BT_OPTION 0x10 + +/* For debug */ +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_CustomerID_8188E 0x00 +#define EEPROM_Default_SubCustomerID 0xCD +#define EEPROM_Default_Version 0 + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPA 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_NCC 0xB +#define EEPROM_USB_OPTIONAL1 0xE +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_CCX 0x10 /* CCX test. */ +#define EEPROM_CID_QMI 0x0D +#define EEPROM_CID_WHQL 0xFE +#define RTL_EEPROM_ID 0x8129 + +#endif /* __RTL8188E_SPEC_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtl8188e_xmit.h b/drivers/staging/rtl8188eu/include/rtl8188e_xmit.h new file mode 100644 index 0000000..20d3548 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtl8188e_xmit.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTL8188E_XMIT_H__ +#define __RTL8188E_XMIT_H__ + +#define MAX_TX_AGG_PACKET_NUMBER 0xFF +/* */ +/* Queue Select Value in TxDesc */ +/* */ +#define QSLT_BK 0x2/* 0x01 */ +#define QSLT_BE 0x0 +#define QSLT_VI 0x5/* 0x4 */ +#define QSLT_VO 0x7/* 0x6 */ +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +/* For 88e early mode */ +#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) +#define SET_EARLYMODE_LEN0(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) +#define SET_EARLYMODE_LEN1(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) +#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) +#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) +#define SET_EARLYMODE_LEN3(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) +#define SET_EARLYMODE_LEN4(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) + +/* */ +/* defined for TX DESC Operation */ +/* */ + +#define MAX_TID (15) + +/* OFFSET 0 */ +#define OFFSET_SZ 0 +#define OFFSET_SHT 16 +#define BMC BIT(24) +#define LSG BIT(26) +#define FSG BIT(27) +#define OWN BIT(31) + + +/* OFFSET 4 */ +#define PKT_OFFSET_SZ 0 +#define QSEL_SHT 8 +#define RATE_ID_SHT 16 +#define NAVUSEHDR BIT(20) +#define SEC_TYPE_SHT 22 +#define PKT_OFFSET_SHT 26 + +/* OFFSET 8 */ +#define AGG_EN BIT(12) +#define AGG_BK BIT(16) +#define AMPDU_DENSITY_SHT 20 +#define ANTSEL_A BIT(24) +#define ANTSEL_B BIT(25) +#define TX_ANT_CCK_SHT 26 +#define TX_ANTL_SHT 28 +#define TX_ANT_HT_SHT 30 + +/* OFFSET 12 */ +#define SEQ_SHT 16 +#define EN_HWSEQ BIT(31) + +/* OFFSET 16 */ +#define QOS BIT(6) +#define HW_SSN BIT(7) +#define USERATE BIT(8) +#define DISDATAFB BIT(10) +#define CTS_2_SELF BIT(11) +#define RTS_EN BIT(12) +#define HW_RTS_EN BIT(13) +#define DATA_SHORT BIT(24) +#define PWR_STATUS_SHT 15 +#define DATA_SC_SHT 20 +#define DATA_BW BIT(25) + +/* OFFSET 20 */ +#define RTY_LMT_EN BIT(17) + +enum TXDESC_SC { + SC_DONT_CARE = 0x00, + SC_UPPER = 0x01, + SC_LOWER = 0x02, + SC_DUPLICATE = 0x03 +}; +/* OFFSET 20 */ +#define SGI BIT(6) +#define USB_TXAGG_NUM_SHT 24 + +#define txdesc_set_ccx_sw_88e(txdesc, value) \ + do { \ + ((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \ + ((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \ + } while (0) + +struct txrpt_ccx_88e { + /* offset 0 */ + u8 tag1:1; + u8 pkt_num:3; + u8 txdma_underflow:1; + u8 int_bt:1; + u8 int_tri:1; + u8 int_ccx:1; + + /* offset 1 */ + u8 mac_id:6; + u8 pkt_ok:1; + u8 bmc:1; + + /* offset 2 */ + u8 retry_cnt:6; + u8 lifetime_over:1; + u8 retry_over:1; + + /* offset 3 */ + u8 ccx_qtime0; + u8 ccx_qtime1; + + /* offset 5 */ + u8 final_data_rate; + + /* offset 6 */ + u8 sw1:4; + u8 qsel:4; + + /* offset 7 */ + u8 sw0; +}; + +#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) +#define txrpt_ccx_qtime_88e(txrpt_ccx) \ + ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) + +void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc, + u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); +s32 rtl8188eu_init_xmit_priv(struct adapter *padapter); +s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter); +#define hal_xmit_handler rtl8188eu_xmit_buf_handler +void rtl8188eu_xmit_tasklet(void *priv); +s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, + struct xmit_priv *pxmitpriv); + +void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf); + +void _dbg_dump_tx_info(struct adapter *padapter, int frame_tag, + struct tx_desc *ptxdesc); + +#endif /* __RTL8188E_XMIT_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_android.h b/drivers/staging/rtl8188eu/include/rtw_android.h new file mode 100644 index 0000000..d7ca7c2 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_android.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ + +#ifndef __RTW_ANDROID_H__ +#define __RTW_ANDROID_H__ + +#include <linux/module.h> +#include <linux/netdevice.h> + +enum ANDROID_WIFI_CMD { + ANDROID_WIFI_CMD_START, + ANDROID_WIFI_CMD_STOP, + ANDROID_WIFI_CMD_SCAN_ACTIVE, + ANDROID_WIFI_CMD_SCAN_PASSIVE, + ANDROID_WIFI_CMD_RSSI, + ANDROID_WIFI_CMD_LINKSPEED, + ANDROID_WIFI_CMD_RXFILTER_START, + ANDROID_WIFI_CMD_RXFILTER_STOP, + ANDROID_WIFI_CMD_RXFILTER_ADD, + ANDROID_WIFI_CMD_RXFILTER_REMOVE, + ANDROID_WIFI_CMD_BTCOEXSCAN_START, + ANDROID_WIFI_CMD_BTCOEXSCAN_STOP, + ANDROID_WIFI_CMD_BTCOEXMODE, + ANDROID_WIFI_CMD_SETSUSPENDOPT, + ANDROID_WIFI_CMD_P2P_DEV_ADDR, + ANDROID_WIFI_CMD_SETFWPATH, + ANDROID_WIFI_CMD_SETBAND, + ANDROID_WIFI_CMD_GETBAND, + ANDROID_WIFI_CMD_COUNTRY, + ANDROID_WIFI_CMD_P2P_SET_NOA, + ANDROID_WIFI_CMD_P2P_GET_NOA, + ANDROID_WIFI_CMD_P2P_SET_PS, + ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE, + ANDROID_WIFI_CMD_MACADDR, + ANDROID_WIFI_CMD_BLOCK, + ANDROID_WIFI_CMD_WFD_ENABLE, + ANDROID_WIFI_CMD_WFD_DISABLE, + ANDROID_WIFI_CMD_WFD_SET_TCPPORT, + ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT, + ANDROID_WIFI_CMD_WFD_SET_DEVTYPE, + ANDROID_WIFI_CMD_MAX +}; + +int rtw_android_cmdstr_to_num(char *cmdstr); +int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd); + +#endif /* __RTW_ANDROID_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_ap.h b/drivers/staging/rtl8188eu/include/rtw_ap.h new file mode 100644 index 0000000..bc0bf20 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_ap.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_AP_H_ +#define __RTW_AP_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +#ifdef CPTCFG_88EU_AP_MODE + +/* external function */ +void rtw_indicate_sta_assoc_event(struct adapter *padapter, + struct sta_info *psta); +void rtw_indicate_sta_disassoc_event(struct adapter *padapter, + struct sta_info *psta); +void init_mlme_ap_info(struct adapter *padapter); +void free_mlme_ap_info(struct adapter *padapter); +void update_beacon(struct adapter *padapter, u8 ie_id, + u8 *oui, u8 tx); +void add_RATid(struct adapter *padapter, struct sta_info *psta, + u8 rssi_level); +void expire_timeout_chk(struct adapter *padapter); +void update_sta_info_apmode(struct adapter *padapter, struct sta_info *psta); +int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len); +void rtw_set_macaddr_acl(struct adapter *padapter, int mode); +int rtw_acl_add_sta(struct adapter *padapter, u8 *addr); +int rtw_acl_remove_sta(struct adapter *padapter, u8 *addr); + +void associated_clients_update(struct adapter *padapter, u8 updated); +void bss_cap_update_on_sta_join(struct adapter *padapter, struct sta_info *psta); +u8 bss_cap_update_on_sta_leave(struct adapter *padapter, struct sta_info *psta); +void sta_info_update(struct adapter *padapter, struct sta_info *psta); +void ap_sta_info_defer_update(struct adapter *padapter, struct sta_info *psta); +u8 ap_free_sta(struct adapter *padapter, struct sta_info *psta, + bool active, u16 reason); +int rtw_sta_flush(struct adapter *padapter); +void start_ap_mode(struct adapter *padapter); +void stop_ap_mode(struct adapter *padapter); +#endif /* end of CPTCFG_88EU_AP_MODE */ + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtw_cmd.h b/drivers/staging/rtl8188eu/include/rtw_cmd.h new file mode 100644 index 0000000..216d711 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_cmd.h @@ -0,0 +1,384 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_CMD_H_ +#define __RTW_CMD_H_ + +#include <wlan_bssdef.h> +#include <rtw_rf.h> +#include <rtw_led.h> + +#include <osdep_service.h> +#include <ieee80211.h> /* <ieee80211/ieee80211.h> */ + +#define MAX_CMDSZ 1024 +#define MAX_RSPSZ 512 + +#define CMDBUFF_ALIGN_SZ 512 + +struct cmd_obj { + struct adapter *padapter; + u16 cmdcode; + u8 res; + u8 *parmbuf; + u32 cmdsz; + u8 *rsp; + u32 rspsz; + struct list_head list; +}; + +struct cmd_priv { + struct completion cmd_queue_comp; + struct completion terminate_cmdthread_comp; + struct __queue cmd_queue; + u8 cmdthd_running; + struct adapter *padapter; +}; + +#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ +do {\ + INIT_LIST_HEAD(&pcmd->list);\ + pcmd->cmdcode = code;\ + pcmd->parmbuf = (u8 *)(pparm);\ + pcmd->cmdsz = sizeof(*pparm);\ + pcmd->rsp = NULL;\ + pcmd->rspsz = 0;\ +} while (0) + +u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); +struct cmd_obj *rtw_dequeue_cmd(struct __queue *queue); +void rtw_free_cmd_obj(struct cmd_obj *pcmd); + +int rtw_cmd_thread(void *context); + +int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv); + +enum rtw_drvextra_cmd_id { + NONE_WK_CID, + DYNAMIC_CHK_WK_CID, + DM_CTRL_WK_CID, + PBC_POLLING_WK_CID, + POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */ + LPS_CTRL_WK_CID, + ANT_SELECT_WK_CID, + P2P_PS_WK_CID, + P2P_PROTO_WK_CID, + CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */ + INTEl_WIDI_WK_CID, + C2H_WK_CID, + RTP_TIMER_CFG_WK_CID, + MAX_WK_CID +}; + +enum LPS_CTRL_TYPE { + LPS_CTRL_SCAN = 0, + LPS_CTRL_JOINBSS = 1, + LPS_CTRL_CONNECT = 2, + LPS_CTRL_DISCONNECT = 3, + LPS_CTRL_SPECIAL_PACKET = 4, + LPS_CTRL_LEAVE = 5, +}; + +enum RFINTFS { + SWSI, + HWSI, + HWPI, +}; + +/* + * Caller Mode: Infra, Ad-HoC(C) + * + * Notes: To disconnect the current associated BSS + * + * Command Mode + * + */ +struct disconnect_parm { + u32 deauth_timeout_ms; +}; + +struct setopmode_parm { + u8 mode; + u8 rsvd[3]; +}; + +/* + * Caller Mode: AP, Ad-HoC, Infra + * + * Notes: To ask RTL8711 performing site-survey + * + * Command-Event Mode + * + */ + +#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */ +#define RTW_CHANNEL_SCAN_AMOUNT (14+37) +struct sitesurvey_parm { + int scan_mode; /* active: 1, passive: 0 */ + u8 ssid_num; + u8 ch_num; + struct ndis_802_11_ssid ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; +}; + +/* + * Caller Mode: Any + * + * Notes: To set the auth type of RTL8711. open/shared/802.1x + * + * Command Mode + * + */ +struct setauth_parm { + u8 mode; /* 0: legacy open, 1: legacy shared 2: 802.1x */ + u8 _1x; /* 0: PSK, 1: TLS */ + u8 rsvd[2]; +}; + +/* + * Caller Mode: Infra + * + * a. algorithm: wep40, wep104, tkip & aes + * b. keytype: grp key/unicast key + * c. key contents + * + * when shared key ==> keyid is the camid + * when 802.1x ==> keyid [0:1] ==> grp key + * when 802.1x ==> keyid > 2 ==> unicast key + * + */ +struct setkey_parm { + u8 algorithm; /* could be none, wep40, TKIP, CCMP, wep104 */ + u8 keyid; + u8 grpkey; /* 1: this is the grpkey for 802.1x. + * 0: this is the unicast key for 802.1x + */ + u8 set_tx; /* 1: main tx key for wep. 0: other key. */ + u8 key[16]; /* this could be 40 or 104 */ +}; + +/* + * When in AP or Ad-Hoc mode, this is used to + * allocate an sw/hw entry for a newly associated sta. + * + * Command + * + * when shared key ==> algorithm/keyid + * + */ +struct set_stakey_parm { + u8 addr[ETH_ALEN]; + u8 algorithm; + u8 id;/* currently for erasing cam entry if + * algorithm == _NO_PRIVACY_ + */ + u8 key[16]; +}; + +struct set_stakey_rsp { + u8 addr[ETH_ALEN]; + u8 keyid; + u8 rsvd; +}; + +/* + * Caller Ad-Hoc/AP + * + * Command -Rsp(AID == CAMID) mode + * + * This is to force fw to add an sta_data entry per driver's request. + * + * FW will write an cam entry associated with it. + * + */ +struct set_assocsta_parm { + u8 addr[ETH_ALEN]; +}; + +struct set_assocsta_rsp { + u8 cam_id; + u8 rsvd[3]; +}; + +/* + * Notes: This command is used for H2C/C2H loopback testing + * + * mac[0] == 0 + * ==> CMD mode, return H2C_SUCCESS. + * The following condition must be true under CMD mode + * mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0; + * s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7; + * s2 == (b1 << 8 | b0); + * + * mac[0] == 1 + * ==> CMD_RSP mode, return H2C_SUCCESS_RSP + * + * The rsp layout shall be: + * rsp: parm: + * mac[0] = mac[5]; + * mac[1] = mac[4]; + * mac[2] = mac[3]; + * mac[3] = mac[2]; + * mac[4] = mac[1]; + * mac[5] = mac[0]; + * s0 = s1; + * s1 = swap16(s0); + * w0 = swap32(w1); + * b0 = b1 + * s2 = s0 + s1 + * b1 = b0 + * w1 = w0 + * + * mac[0] == 2 + * ==> CMD_EVENT mode, return H2C_SUCCESS + * The event layout shall be: + * event: parm: + * mac[0] = mac[5]; + * mac[1] = mac[4]; + * mac[2] = event's seq no, starting from 1 to parm's marc[3] + * mac[2] = event's seq no, starting from 1 to parm's marc[3] + * mac[2] = event's seq no, starting from 1 to parm's marc[3] + * mac[3] = mac[2]; + * mac[4] = mac[1]; + * mac[5] = mac[0]; + * s0 = swap16(s0) - event.mac[2]; + * s1 = s1 + event.mac[2]; + * w0 = swap32(w0); + * b0 = b1 + * s2 = s0 + event.mac[2] + * b1 = b0 + * w1 = swap32(w1) - event.mac[2]; + * + * parm->mac[3] is the total event counts that host requested. + * event will be the same with the cmd's param. + */ + +/* CMD param Format for driver extra cmd handler */ +struct drvextra_cmd_parm { + int ec_id; /* extra cmd id */ + int type_size; /* Can use this field as the type id or command size */ + unsigned char *pbuf; +}; + +struct addBaReq_parm { + unsigned int tid; + u8 addr[ETH_ALEN]; +}; + +/*H2C Handler index: 46 */ +struct set_ch_parm { + u8 ch; + u8 bw; + u8 ch_offset; +}; + +/*H2C Handler index: 59 */ +struct SetChannelPlan_param { + u8 channel_plan; +}; + +/* + * + * Result: + * 0x00: success + * 0x01: success, and check Response. + * 0x02: cmd ignored due to duplicated sequcne number + * 0x03: cmd dropped due to invalid cmd code + * 0x04: reserved. + * + */ + +#define H2C_SUCCESS 0x00 +#define H2C_SUCCESS_RSP 0x01 +#define H2C_DROPPED 0x03 +#define H2C_PARAMETERS_ERROR 0x04 +#define H2C_REJECTED 0x05 + +u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, + int ssid_num, struct rtw_ieee80211_channel *ch, + int ch_num); +u8 rtw_createbss_cmd(struct adapter *padapter); +u8 rtw_setstakey_cmd(struct adapter *padapter, u8 *psta, u8 unicast_key); +u8 rtw_clearstakey_cmd(struct adapter *padapter, u8 *psta, u8 entry, + u8 enqueue); +u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork); +u8 rtw_disassoc_cmd(struct adapter *padapter, u32 deauth_timeout_ms, + bool enqueue); +u8 rtw_setopmode_cmd(struct adapter *padapter, + enum ndis_802_11_network_infra networktype); +u8 rtw_addbareq_cmd(struct adapter *padapter, u8 tid, u8 *addr); + +u8 rtw_dynamic_chk_wk_cmd(struct adapter *adapter); + +u8 rtw_lps_ctrl_wk_cmd(struct adapter *padapter, u8 lps_ctrl_type, u8 enqueue); +u8 rtw_rpt_timer_cfg_cmd(struct adapter *padapter, u16 minRptTime); + +u8 rtw_antenna_select_cmd(struct adapter *padapter, u8 antenna, u8 enqueue); +u8 rtw_ps_cmd(struct adapter *padapter); + +#ifdef CPTCFG_88EU_AP_MODE +u8 rtw_chk_hi_queue_cmd(struct adapter *padapter); +#endif + +u8 rtw_set_chplan_cmd(struct adapter *padapter, u8 chplan, u8 enqueue); +u8 rtw_drvextra_cmd_hdl(struct adapter *padapter, unsigned char *pbuf); + +void rtw_survey_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_disassoc_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_createbss_cmd_callback(struct adapter *adapt, struct cmd_obj *pcmd); +void rtw_readtssi_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd); + +void rtw_setstaKey_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd); +void rtw_setassocsta_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cm); +void rtw_getrttbl_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd); + +struct _cmd_callback { + u32 cmd_code; + void (*callback)(struct adapter *padapter, struct cmd_obj *cmd); +}; + +enum rtw_h2c_cmd { + _JoinBss_CMD_, + _DisConnect_CMD_, + _CreateBss_CMD_, + _SetOpMode_CMD_, + _SiteSurvey_CMD_, + _SetAuth_CMD_, + _SetKey_CMD_, + _SetStaKey_CMD_, + _SetAssocSta_CMD_, + _AddBAReq_CMD_, + _SetChannel_CMD_, + _TX_Beacon_CMD_, + _Set_MLME_EVT_CMD_, + _Set_Drv_Extra_CMD_, + _SetChannelPlan_CMD_, + + MAX_H2CCMD +}; + +#ifdef _RTW_CMD_C_ +static struct _cmd_callback rtw_cmd_callback[] = { + {_JoinBss_CMD_, &rtw_joinbss_cmd_callback}, + {_DisConnect_CMD_, &rtw_disassoc_cmd_callback}, + {_CreateBss_CMD_, &rtw_createbss_cmd_callback}, + {_SetOpMode_CMD_, NULL}, + {_SiteSurvey_CMD_, &rtw_survey_cmd_callback}, + {_SetAuth_CMD_, NULL}, + {_SetKey_CMD_, NULL}, + {_SetStaKey_CMD_, &rtw_setstaKey_cmdrsp_callback}, + {_SetAssocSta_CMD_, &rtw_setassocsta_cmdrsp_callback}, + {_AddBAReq_CMD_, NULL}, + {_SetChannel_CMD_, NULL}, + {_TX_Beacon_CMD_, NULL}, + {_Set_MLME_EVT_CMD_, NULL}, + {_Set_Drv_Extra_CMD_, NULL}, + {_SetChannelPlan_CMD_, NULL}, +}; +#endif + +#endif /* _CMD_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_debug.h b/drivers/staging/rtl8188eu/include/rtw_debug.h new file mode 100644 index 0000000..9840e59 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_debug.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_DEBUG_H__ +#define __RTW_DEBUG_H__ + +#include <osdep_service.h> +#include <drv_types.h> + +#define DRIVERVERSION "v4.1.4_6773.20130222" +#define _drv_always_ 1 +#define _drv_emerg_ 2 +#define _drv_alert_ 3 +#define _drv_crit_ 4 +#define _drv_err_ 5 +#define _drv_warning_ 6 +#define _drv_notice_ 7 +#define _drv_info_ 8 +#define _drv_debug_ 9 + + +#define _module_rtl871x_xmit_c_ BIT(0) +#define _module_xmit_osdep_c_ BIT(1) +#define _module_rtl871x_recv_c_ BIT(2) +#define _module_recv_osdep_c_ BIT(3) +#define _module_rtl871x_mlme_c_ BIT(4) +#define _module_mlme_osdep_c_ BIT(5) +#define _module_rtl871x_sta_mgt_c_ BIT(6) +#define _module_rtl871x_cmd_c_ BIT(7) +#define _module_cmd_osdep_c_ BIT(8) +#define _module_rtl871x_io_c_ BIT(9) +#define _module_io_osdep_c_ BIT(10) +#define _module_os_intfs_c_ BIT(11) +#define _module_rtl871x_security_c_ BIT(12) +#define _module_rtl871x_eeprom_c_ BIT(13) +#define _module_hal_init_c_ BIT(14) +#define _module_hci_hal_init_c_ BIT(15) +#define _module_rtl871x_ioctl_c_ BIT(16) +#define _module_rtl871x_ioctl_set_c_ BIT(17) +#define _module_rtl871x_ioctl_query_c_ BIT(18) +#define _module_rtl871x_pwrctrl_c_ BIT(19) +#define _module_hci_intfs_c_ BIT(20) +#define _module_hci_ops_c_ BIT(21) +#define _module_osdep_service_c_ BIT(22) +#define _module_mp_ BIT(23) +#define _module_hci_ops_os_c_ BIT(24) +#define _module_rtl871x_ioctl_os_c BIT(25) +#define _module_rtl8712_cmd_c_ BIT(26) +#define _module_rtl8192c_xmit_c_ BIT(27) +#define _module_hal_xmit_c_ BIT(28) +#define _module_efuse_ BIT(29) +#define _module_rtl8712_recv_c_ BIT(30) +#define _module_rtl8712_led_c_ BIT(31) + +#define DRIVER_PREFIX "R8188EU: " + +extern u32 GlobalDebugLevel; + +#define DBG_88E_LEVEL(_level, fmt, arg...) \ + do { \ + if (_level <= GlobalDebugLevel) \ + pr_info(DRIVER_PREFIX fmt, ##arg); \ + } while (0) + +#define DBG_88E(...) \ + do { \ + if (_drv_err_ <= GlobalDebugLevel) \ + pr_info(DRIVER_PREFIX __VA_ARGS__); \ + } while (0) + +#define MSG_88E(...) \ + do { \ + if (_drv_err_ <= GlobalDebugLevel) \ + pr_info(DRIVER_PREFIX __VA_ARGS__); \ + } while (0) + +#define RT_TRACE(_comp, _level, fmt) \ + do { \ + if (_level <= GlobalDebugLevel) { \ + pr_info("%s [0x%08x,%d]", DRIVER_PREFIX, \ + (unsigned int)_comp, _level); \ + pr_info fmt; \ + } \ + } while (0) + +#define RT_PRINT_DATA(_comp, _level, _titlestring, _hexdata, _hexdatalen)\ + do { \ + if (_level <= GlobalDebugLevel) { \ + int __i; \ + u8 *ptr = (u8 *)_hexdata; \ + pr_info("%s", DRIVER_PREFIX); \ + pr_info(_titlestring); \ + for (__i = 0; __i < (int)_hexdatalen; __i++) { \ + pr_info("%02X%s", ptr[__i], \ + (((__i + 1) % 4) == 0) ? \ + " " : " "); \ + if (((__i + 1) % 16) == 0) \ + pr_cont("\n"); \ + } \ + pr_cont("\n"); \ + } \ + } while (0) + +int proc_get_drv_version(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_write_reg(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_set_write_reg(struct file *file, const char __user *buffer, + unsigned long count, void *data); +int proc_get_read_reg(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_set_read_reg(struct file *file, const char __user *buffer, + unsigned long count, void *data); + +int proc_get_adapter_state(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_best_channel(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +#endif /* __RTW_DEBUG_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_eeprom.h b/drivers/staging/rtl8188eu/include/rtw_eeprom.h new file mode 100644 index 0000000..db25eb5 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_eeprom.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_EEPROM_H__ +#define __RTW_EEPROM_H__ + +#include <osdep_service.h> +#include <drv_types.h> + +#define RTL8712_EEPROM_ID 0x8712 + +#define HWSET_MAX_SIZE_512 512 +#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512 + +#define CLOCK_RATE 50 /* 100us */ + +/* EEPROM opcodes */ +#define EEPROM_READ_OPCODE 06 +#define EEPROM_WRITE_OPCODE 05 +#define EEPROM_ERASE_OPCODE 07 +#define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */ +#define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */ + +/* Country codes */ +#define USA 0x555320 +#define EUROPE 0x1 /* temp, should be provided later */ +#define JAPAN 0x2 /* temp, should be provided later */ + +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_ALPHA 0x1 +#define EEPROM_CID_Senao 0x3 +#define EEPROM_CID_NetCore 0x5 +#define EEPROM_CID_CAMEO 0X8 +#define EEPROM_CID_SITECOM 0x9 +#define EEPROM_CID_COREGA 0xB +#define EEPROM_CID_EDIMAX_BELK 0xC +#define EEPROM_CID_SERCOMM_BELK 0xE +#define EEPROM_CID_CAMEO1 0xF +#define EEPROM_CID_WNC_COREGA 0x12 +#define EEPROM_CID_CLEVO 0x13 +#define EEPROM_CID_WHQL 0xFE + +/* Customer ID, note that: */ +/* This variable is initiailzed through EEPROM or registry, */ +/* however, its definition may be different with that in EEPROM for */ +/* EEPROM size consideration. So, we have to perform proper translation + * between them. + */ +/* Besides, CustomerID of registry has precedence of that of EEPROM. */ +/* defined below. 060703, by rcnjko. */ +enum RT_CUSTOMER_ID { + RT_CID_DEFAULT = 0, + RT_CID_8187_ALPHA0 = 1, + RT_CID_8187_SERCOMM_PS = 2, + RT_CID_8187_HW_LED = 3, + RT_CID_8187_NETGEAR = 4, + RT_CID_WHQL = 5, + RT_CID_819x_CAMEO = 6, + RT_CID_819x_RUNTOP = 7, + RT_CID_819x_Senao = 8, + RT_CID_TOSHIBA = 9, /* Merge by Jacken, 2008/01/31. */ + RT_CID_819x_Netcore = 10, + RT_CID_Nettronix = 11, + RT_CID_DLINK = 12, + RT_CID_PRONET = 13, + RT_CID_COREGA = 14, + RT_CID_CHINA_MOBILE = 15, + RT_CID_819x_ALPHA = 16, + RT_CID_819x_Sitecom = 17, + RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded + * for CCX functions, but for test behavior like retry + * limit and tx report. By Bruce, 2009-02-17. + */ + RT_CID_819x_Lenovo = 19, + RT_CID_819x_QMI = 20, + RT_CID_819x_Edimax_Belkin = 21, + RT_CID_819x_Sercomm_Belkin = 22, + RT_CID_819x_CAMEO1 = 23, + RT_CID_819x_MSI = 24, + RT_CID_819x_Acer = 25, + RT_CID_819x_AzWave_ASUS = 26, + RT_CID_819x_AzWave = 27, /* For AzWave in PCIe,i + * The ID is AzWave use and not only Asus + */ + RT_CID_819x_HP = 28, + RT_CID_819x_WNC_COREGA = 29, + RT_CID_819x_Arcadyan_Belkin = 30, + RT_CID_819x_SAMSUNG = 31, + RT_CID_819x_CLEVO = 32, + RT_CID_819x_DELL = 33, + RT_CID_819x_PRONETS = 34, + RT_CID_819x_Edimax_ASUS = 35, + RT_CID_819x_CAMEO_NETGEAR = 36, + RT_CID_PLANEX = 37, + RT_CID_CC_C = 38, + RT_CID_819x_Xavi = 39, + RT_CID_819x_FUNAI_TV = 40, + RT_CID_819x_ALPHA_WD = 41, +}; + +struct eeprom_priv { + u8 bautoload_fail_flag; + u8 bloadfile_fail_flag; + u8 bloadmac_fail_flag; + u8 mac_addr[6]; /* PermanentAddress */ + u16 channel_plan; + u8 EepromOrEfuse; + u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; +}; + +void eeprom_write16(struct adapter *padapter, u16 reg, u16 data); +u16 eeprom_read16(struct adapter *padapter, u16 reg); +void read_eeprom_content(struct adapter *padapter); +void eeprom_read_sz(struct adapter *adapt, u16 reg, u8 *data, u32 sz); +void read_eeprom_content_by_attrib(struct adapter *padapter); + +#endif /* __RTL871X_EEPROM_H__ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_efuse.h b/drivers/staging/rtl8188eu/include/rtw_efuse.h new file mode 100644 index 0000000..3ec5376 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_efuse.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_EFUSE_H__ +#define __RTW_EFUSE_H__ + +#include <osdep_service.h> + +#define EFUSE_ERROE_HANDLE 1 + +#define PG_STATE_HEADER 0x01 +#define PG_STATE_WORD_0 0x02 +#define PG_STATE_WORD_1 0x04 +#define PG_STATE_WORD_2 0x08 +#define PG_STATE_WORD_3 0x10 +#define PG_STATE_DATA 0x20 + +#define PG_SWBYTE_H 0x01 +#define PG_SWBYTE_L 0x02 + +#define PGPKT_DATA_SIZE 8 + +#define EFUSE_WIFI 0 +#define EFUSE_BT 1 + +/* E-Fuse */ +#define EFUSE_MAP_SIZE 512 +#define EFUSE_MAX_SIZE 256 +/* end of E-Fuse */ + +#define EFUSE_MAX_MAP_LEN 512 +#define EFUSE_MAX_HW_SIZE 512 +#define EFUSE_MAX_SECTION_BASE 16 + +#define EXT_HEADER(header) ((header & 0x1F) == 0x0F) +#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) +#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5) + +#define EFUSE_REPEAT_THRESHOLD_ 3 + +/* The following is for BT Efuse definition */ +#define EFUSE_BT_MAX_MAP_LEN 1024 +#define EFUSE_MAX_BANK 4 +#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) +/*--------------------------Define Parameters-------------------------------*/ +#define EFUSE_MAX_WORD_UNIT 4 + +/*------------------------------Define structure----------------------------*/ +struct pgpkt { + u8 offset; + u8 word_en; + u8 data[8]; + u8 word_cnts; +}; + +/*------------------------------Define structure----------------------------*/ +struct efuse_hal { + u8 fakeEfuseBank; + u32 fakeEfuseUsedBytes; + u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]; + u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; + u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; + + u16 BTEfuseUsedBytes; + u8 BTEfuseUsedPercentage; + u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + u16 fakeBTEfuseUsedBytes; + u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; +}; + +u8 Efuse_CalculateWordCnts(u8 word_en); +u8 efuse_OneByteRead(struct adapter *adapter, u16 addr, u8 *data); +u8 efuse_OneByteWrite(struct adapter *adapter, u16 addr, u8 data); + +void efuse_ReadEFuse(struct adapter *Adapter, u8 efuseType, u16 _offset, + u16 _size_byte, u8 *pbuf); +void efuse_power_switch(struct adapter *adapt, u8 write, u8 pwrstate); +int Efuse_PgPacketRead(struct adapter *adapt, u8 offset, u8 *data); +bool Efuse_PgPacketWrite(struct adapter *adapter, u8 offset, u8 word, u8 *data); +void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); +u8 Efuse_WordEnableDataWrite(struct adapter *adapter, u16 efuse_addr, + u8 word_en, u8 *data); + +void EFUSE_ShadowMapUpdate(struct adapter *adapter, u8 efusetype); +#endif diff --git a/drivers/staging/rtl8188eu/include/rtw_event.h b/drivers/staging/rtl8188eu/include/rtw_event.h new file mode 100644 index 0000000..bfe774e --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_event.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _RTW_EVENT_H_ +#define _RTW_EVENT_H_ + +#include <osdep_service.h> + +#include <wlan_bssdef.h> +#include <linux/mutex.h> +#include <linux/sem.h> + +/* + * Used to report a bss has been scanned + */ +struct survey_event { + struct wlan_bssid_ex bss; +}; + +/* + * Used to report that the requested site survey has been done. + * + * bss_cnt indicates the number of bss that has been reported. + * + * + */ +struct surveydone_event { + unsigned int bss_cnt; + +}; + +/* + * Used to report the link result of joinning the given bss + * + * + * join_res: + * -1: authentication fail + * -2: association fail + * > 0: TID + * + */ +struct joinbss_event { + struct wlan_network network; +}; + +/* + * Used to report a given STA has joinned the created BSS. + * It is used in AP/Ad-HoC(M) mode. + */ + +struct stassoc_event { + unsigned char macaddr[6]; + unsigned char rsvd[2]; + int cam_id; +}; + +struct stadel_event { + unsigned char macaddr[6]; + unsigned char rsvd[2]; /* for reason */ + int mac_id; +}; + +struct fwevent { + u32 parmsize; + void (*event_callback)(struct adapter *dev, u8 *pbuf); +}; + +#define C2HEVENT_SZ 32 + +#define NETWORK_QUEUE_SZ 4 + +struct network_queue { + int head; + int tail; + struct wlan_bssid_ex networks[NETWORK_QUEUE_SZ]; +}; + +#endif /* _WLANEVENT_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_ht.h b/drivers/staging/rtl8188eu/include/rtw_ht.h new file mode 100644 index 0000000..192fa50 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_ht.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _RTW_HT_H_ +#define _RTW_HT_H_ + +#include <linux/ieee80211.h> + +struct ht_priv { + u32 ht_option; + u32 ampdu_enable;/* for enable Tx A-MPDU */ + u8 bwmode;/* */ + u8 ch_offset;/* PRIME_CHNL_OFFSET */ + u8 sgi;/* short GI */ + + /* for processing Tx A-MPDU */ + u8 agg_enable_bitmap; + u8 candidate_tid_bitmap; + + struct ieee80211_ht_cap ht_cap; +}; + +#endif /* _RTL871X_HT_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_ioctl.h b/drivers/staging/rtl8188eu/include/rtw_ioctl.h new file mode 100644 index 0000000..5d773c8 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_ioctl.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _RTW_IOCTL_H_ +#define _RTW_IOCTL_H_ + +#include <osdep_service.h> +#include <drv_types.h> + + +#ifndef OID_802_11_CAPABILITY + #define OID_802_11_CAPABILITY 0x0d010122 +#endif + +#ifndef OID_802_11_PMKID + #define OID_802_11_PMKID 0x0d010123 +#endif + + +/* For DDK-defined OIDs */ +#define OID_NDIS_SEG1 0x00010100 +#define OID_NDIS_SEG2 0x00010200 +#define OID_NDIS_SEG3 0x00020100 +#define OID_NDIS_SEG4 0x01010100 +#define OID_NDIS_SEG5 0x01020100 +#define OID_NDIS_SEG6 0x01020200 +#define OID_NDIS_SEG7 0xFD010100 +#define OID_NDIS_SEG8 0x0D010100 +#define OID_NDIS_SEG9 0x0D010200 +#define OID_NDIS_SEG10 0x0D020200 + +#define SZ_OID_NDIS_SEG1 23 +#define SZ_OID_NDIS_SEG2 3 +#define SZ_OID_NDIS_SEG3 6 +#define SZ_OID_NDIS_SEG4 6 +#define SZ_OID_NDIS_SEG5 4 +#define SZ_OID_NDIS_SEG6 8 +#define SZ_OID_NDIS_SEG7 7 +#define SZ_OID_NDIS_SEG8 36 +#define SZ_OID_NDIS_SEG9 24 +#define SZ_OID_NDIS_SEG10 19 + +/* For Realtek-defined OIDs */ +#define OID_MP_SEG1 0xFF871100 +#define OID_MP_SEG2 0xFF818000 + +#define OID_MP_SEG3 0xFF818700 +#define OID_MP_SEG4 0xFF011100 + +enum oid_type { + QUERY_OID, + SET_OID +}; + +struct oid_par_priv { + void *adapter_context; + NDIS_OID oid; + void *information_buf; + u32 information_buf_len; + u32 *bytes_rw; + u32 *bytes_needed; + enum oid_type type_of_oid; + u32 dbg; +}; + +#if defined(_RTW_MP_IOCTL_C_) +static int oid_null_function(struct oid_par_priv *poid_par_priv) +{ + return NDIS_STATUS_SUCCESS; +} +#endif + +extern struct iw_handler_def rtw_handlers_def; + +int drv_query_info(struct net_device *miniportadaptercontext, NDIS_OID oid, + void *informationbuffer, u32 informationbufferlength, + u32 *byteswritten, u32 *bytesneeded); + +int drv_set_info(struct net_device *MiniportAdapterContext, + NDIS_OID oid, void *informationbuffer, + u32 informationbufferlength, u32 *bytesread, + u32 *bytesneeded); + +#endif /* #ifndef __INC_CEINFO_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_ioctl_set.h b/drivers/staging/rtl8188eu/include/rtw_ioctl_set.h new file mode 100644 index 0000000..0be99f6 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_ioctl_set.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_IOCTL_SET_H_ +#define __RTW_IOCTL_SET_H_ + +#include <drv_types.h> + + +typedef u8 NDIS_802_11_PMKID_VALUE[16]; + +u8 rtw_set_802_11_authentication_mode(struct adapter *adapt, + enum ndis_802_11_auth_mode authmode); +u8 rtw_set_802_11_bssid(struct adapter *adapter, u8 *bssid); +u8 rtw_set_802_11_add_wep(struct adapter *adapter, struct ndis_802_11_wep *wep); +u8 rtw_set_802_11_disassociate(struct adapter *adapter); +u8 rtw_set_802_11_bssid_list_scan(struct adapter *adapter, + struct ndis_802_11_ssid *pssid, + int ssid_max_num); +u8 rtw_set_802_11_infrastructure_mode(struct adapter *adapter, + enum ndis_802_11_network_infra type); +u8 rtw_set_802_11_ssid(struct adapter *adapt, struct ndis_802_11_ssid *ssid); +u16 rtw_get_cur_max_rate(struct adapter *adapter); +int rtw_set_country(struct adapter *adapter, const char *country_code); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtw_iol.h b/drivers/staging/rtl8188eu/include/rtw_iol.h new file mode 100644 index 0000000..d713782 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_iol.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_IOL_H_ +#define __RTW_IOL_H_ + +#include <drv_types.h> + +bool rtw_iol_applied(struct adapter *adapter); + +#endif /* __RTW_IOL_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_led.h b/drivers/staging/rtl8188eu/include/rtw_led.h new file mode 100644 index 0000000..e50237a --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_led.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_LED_H_ +#define __RTW_LED_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 +#define LED_BLINK_LINK_INTERVAL_ALPHA 500 /* 500 */ +#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 /* 150 */ +#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 +#define LED_BLINK_WPS_SUCCESS_INTERVAL_ALPHA 5000 + +enum LED_CTL_MODE { + LED_CTL_POWER_ON, + LED_CTL_LINK, + LED_CTL_NO_LINK, + LED_CTL_TX, + LED_CTL_RX, + LED_CTL_SITE_SURVEY, + LED_CTL_POWER_OFF, + LED_CTL_START_TO_LINK, + LED_CTL_START_WPS, + LED_CTL_STOP_WPS, + LED_CTL_START_WPS_BOTTON, + LED_CTL_STOP_WPS_FAIL +}; + +enum LED_STATE_871x { + LED_UNKNOWN, + RTW_LED_ON, + RTW_LED_OFF, + LED_BLINK_NORMAL, + LED_BLINK_SLOWLY, + LED_BLINK_POWER_ON, + LED_BLINK_SCAN, + LED_BLINK_TXRX, + LED_BLINK_WPS, + LED_BLINK_WPS_STOP +}; + +struct LED_871x { + struct adapter *padapter; + + enum LED_STATE_871x CurrLedState; /* Current LED state. */ + enum LED_STATE_871x BlinkingLedState; /* Next state for blinking, + * either RTW_LED_ON or RTW_LED_OFF are. + */ + + u8 bLedOn; /* true if LED is ON, false if LED is OFF. */ + + u8 bLedBlinkInProgress; /* true if it is blinking, false o.w.. */ + + u8 bLedWPSBlinkInProgress; + + u32 BlinkTimes; /* Number of times to toggle led state for blinking. */ + + struct timer_list BlinkTimer; /* Timer object for led blinking. */ + + /* ALPHA, added by chiyoko, 20090106 */ + u8 bLedNoLinkBlinkInProgress; + u8 bLedLinkBlinkInProgress; + u8 bLedScanBlinkInProgress; + struct work_struct BlinkWorkItem; /* Workitem used by BlinkTimer to + * manipulate H/W to blink LED. + */ +}; + +#define IS_LED_WPS_BLINKING(_LED_871x) \ + (((struct LED_871x *)_LED_871x)->CurrLedState == LED_BLINK_WPS || \ + ((struct LED_871x *)_LED_871x)->CurrLedState == LED_BLINK_WPS_STOP || \ + ((struct LED_871x *)_LED_871x)->bLedWPSBlinkInProgress) + +void LedControl8188eu(struct adapter *padapter, enum LED_CTL_MODE LedAction); + +struct led_priv { + /* add for led control */ + struct LED_871x SwLed0; + /* add for led control */ +}; + +void BlinkWorkItemCallback(struct work_struct *work); + +void ResetLedStatus(struct LED_871x *pLed); + +void InitLed871x(struct adapter *padapter, struct LED_871x *pLed); + +void DeInitLed871x(struct LED_871x *pLed); + +/* hal... */ +void BlinkHandler(struct LED_871x *pLed); +void SwLedOn(struct adapter *padapter, struct LED_871x *pLed); +void SwLedOff(struct adapter *padapter, struct LED_871x *pLed); + +#endif /* __RTW_LED_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_mlme.h b/drivers/staging/rtl8188eu/include/rtw_mlme.h new file mode 100644 index 0000000..7456d78 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_mlme.h @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_MLME_H_ +#define __RTW_MLME_H_ + +#include <osdep_service.h> +#include <mlme_osdep.h> +#include <drv_types.h> +#include <wlan_bssdef.h> + +#define MAX_BSS_CNT 128 +#define MAX_JOIN_TIMEOUT 6500 + +/* Increase the scanning timeout because of increasing the SURVEY_TO value. */ + +#define SCANNING_TIMEOUT 8000 + +#define SCAN_INTERVAL (30) /* unit:2sec, 30*2=60sec */ + +#define SCANQUEUE_LIFETIME 20 /* unit:sec */ + +#define WIFI_NULL_STATE 0x00000000 + +#define WIFI_ASOC_STATE 0x00000001 /* Under Linked state */ +#define WIFI_REASOC_STATE 0x00000002 +#define WIFI_SLEEP_STATE 0x00000004 +#define WIFI_STATION_STATE 0x00000008 + +#define WIFI_AP_STATE 0x00000010 +#define WIFI_ADHOC_STATE 0x00000020 +#define WIFI_ADHOC_MASTER_STATE 0x00000040 +#define WIFI_UNDER_LINKING 0x00000080 + +#define WIFI_UNDER_WPS 0x00000100 +#define WIFI_STA_ALIVE_CHK_STATE 0x00000400 +#define WIFI_SITE_MONITOR 0x00000800 /* to indicate the station is under site surveying */ + +#define _FW_UNDER_LINKING WIFI_UNDER_LINKING +#define _FW_LINKED WIFI_ASOC_STATE +#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR + +enum dot11AuthAlgrthmNum { + dot11AuthAlgrthm_Open = 0, /* open system */ + dot11AuthAlgrthm_Shared, + dot11AuthAlgrthm_8021X, + dot11AuthAlgrthm_Auto, + dot11AuthAlgrthm_WAPI, + dot11AuthAlgrthm_MaxNum +}; + +/* Scan type including active and passive scan. */ +enum rt_scan_type { + SCAN_PASSIVE, + SCAN_ACTIVE, + SCAN_MIX, +}; + +enum SCAN_RESULT_TYPE { + SCAN_RESULT_P2P_ONLY = 0, /* Will return all the P2P devices. */ + SCAN_RESULT_ALL = 1, /* Will return all the scanned device, + * include AP. + */ + SCAN_RESULT_WFD_TYPE = 2 /* Will just return the correct WFD + * device. + */ + /* If this device is Miracast sink + * device, it will just return all the + * Miracast source devices. + */ +}; + +/* + * there are several "locks" in mlme_priv, + * since mlme_priv is a shared resource between many threads, + * like ISR/Call-Back functions, the OID handlers, and even timer functions. + * + * Each _queue has its own locks, already. + * Other items are protected by mlme_priv.lock. + * + * To avoid possible dead lock, any thread trying to modifiying mlme_priv + * SHALL not lock up more than one lock at a time! + */ + +#define traffic_threshold 10 +#define traffic_scan_period 500 + +struct rt_link_detect { + u32 NumTxOkInPeriod; + u32 NumRxOkInPeriod; + u32 NumRxUnicastOkInPeriod; + bool bBusyTraffic; + bool bTxBusyTraffic; + bool bRxBusyTraffic; + bool bHigherBusyTraffic; /* For interrupt migration purpose. */ + bool bHigherBusyRxTraffic; /* We may disable Tx interrupt according + * to Rx traffic. + */ + bool bHigherBusyTxTraffic; /* We may disable Tx interrupt according + * to Tx traffic. + */ +}; + +struct mlme_priv { + spinlock_t lock; + int fw_state; /* shall we protect this variable? maybe not necessarily... */ + u8 bScanInProcess; + u8 to_join; /* flag */ + u8 to_roaming; /* roaming trying times */ + + u8 *nic_hdl; + + struct list_head *pscanned; + struct __queue free_bss_pool; + struct __queue scanned_queue; + u8 *free_bss_buf; + + struct ndis_802_11_ssid assoc_ssid; + u8 assoc_bssid[6]; + + struct wlan_network cur_network; + + u32 scan_interval; + + struct timer_list assoc_timer; + + uint assoc_by_bssid; + + struct timer_list scan_to_timer; /* driver itself handles scan_timeout status. */ + + struct qos_priv qospriv; + + /* Number of non-HT AP/stations */ + int num_sta_no_ht; + + /* Number of HT AP/stations 20 MHz */ + /* int num_sta_ht_20mhz; */ + + int num_FortyMHzIntolerant; + struct ht_priv htpriv; + struct rt_link_detect LinkDetectInfo; + struct timer_list dynamic_chk_timer; /* dynamic/periodic check timer */ + + u8 key_mask; /* use for ips to set wep key after ips_leave */ + u8 acm_mask; /* for wmm acm mask */ + u8 ChannelPlan; + enum rt_scan_type scan_mode; /* active: 1, passive: 0 */ + + /* u8 probereq_wpsie[MAX_WPS_IE_LEN];added in probe req */ + /* int probereq_wpsie_len; */ + u8 *wps_probe_req_ie; + u32 wps_probe_req_ie_len; + + u8 *assoc_req; + u32 assoc_req_len; + u8 *assoc_rsp; + u32 assoc_rsp_len; + +#if defined(CPTCFG_88EU_AP_MODE) + /* Number of associated Non-ERP stations (i.e., stations using 802.11b + * in 802.11g BSS) + */ + int num_sta_non_erp; + + /* Number of associated stations that do not support Short Slot Time */ + int num_sta_no_short_slot_time; + + /* Number of associated stations that do not support Short Preamble */ + int num_sta_no_short_preamble; + + int olbc; /* Overlapping Legacy BSS Condition */ + + /* Number of HT assoc sta that do not support greenfield */ + int num_sta_ht_no_gf; + + /* Number of associated non-HT stations */ + /* int num_sta_no_ht; */ + + /* Number of HT associated stations 20 MHz */ + int num_sta_ht_20mhz; + + /* Overlapping BSS information */ + int olbc_ht; + + u16 ht_op_mode; + + u8 *wps_beacon_ie; + /* u8 *wps_probe_req_ie; */ + u8 *wps_probe_resp_ie; + u8 *wps_assoc_resp_ie; + + u32 wps_beacon_ie_len; + u32 wps_probe_resp_ie_len; + u32 wps_assoc_resp_ie_len; + + spinlock_t bcn_update_lock; + u8 update_bcn; +#endif /* if defined (CPTCFG_88EU_AP_MODE) */ +}; + +#ifdef CPTCFG_88EU_AP_MODE + +struct hostapd_priv { + struct adapter *padapter; +}; + +int hostapd_mode_init(struct adapter *padapter); +void hostapd_mode_unload(struct adapter *padapter); +#endif + +extern unsigned char WPA_TKIP_CIPHER[4]; +extern unsigned char RSN_TKIP_CIPHER[4]; +extern unsigned char REALTEK_96B_IE[]; +extern unsigned char MCS_rate_1R[16]; + +void rtw_joinbss_event_prehandle(struct adapter *adapter, u8 *pbuf); +void rtw_survey_event_callback(struct adapter *adapter, u8 *pbuf); +void rtw_surveydone_event_callback(struct adapter *adapter, u8 *pbuf); +void rtw_joinbss_event_callback(struct adapter *adapter, u8 *pbuf); +void rtw_stassoc_event_callback(struct adapter *adapter, u8 *pbuf); +void rtw_stadel_event_callback(struct adapter *adapter, u8 *pbuf); +void rtw_atimdone_event_callback(struct adapter *adapter, u8 *pbuf); +void rtw_cpwm_event_callback(struct adapter *adapter, u8 *pbuf); +void indicate_wx_scan_complete_event(struct adapter *padapter); +void rtw_indicate_wx_assoc_event(struct adapter *padapter); +void rtw_indicate_wx_disassoc_event(struct adapter *padapter); +int event_thread(void *context); +void rtw_free_network_queue(struct adapter *adapter, u8 isfreeall); +int rtw_init_mlme_priv(struct adapter *adapter); +void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv); +int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv); +int rtw_set_key(struct adapter *adapter, struct security_priv *psecuritypriv, + int keyid, u8 set_tx); +int rtw_set_auth(struct adapter *adapter, struct security_priv *psecuritypriv); + +static inline u8 *get_bssid(struct mlme_priv *pmlmepriv) +{ /* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */ + /* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */ + return pmlmepriv->cur_network.network.MacAddress; +} + +static inline int check_fwstate(struct mlme_priv *pmlmepriv, int state) +{ + if (pmlmepriv->fw_state & state) + return true; + + return false; +} + +static inline int get_fwstate(struct mlme_priv *pmlmepriv) +{ + return pmlmepriv->fw_state; +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + * + * ### NOTE:#### (!!!!) + * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock + */ +static inline void set_fwstate(struct mlme_priv *pmlmepriv, int state) +{ + pmlmepriv->fw_state |= state; + /* FOR HW integration */ + if (_FW_UNDER_SURVEY == state) + pmlmepriv->bScanInProcess = true; +} + +static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, int state) +{ + pmlmepriv->fw_state &= ~state; + /* FOR HW integration */ + if (_FW_UNDER_SURVEY == state) + pmlmepriv->bScanInProcess = false; +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + */ +static inline void clr_fwstate(struct mlme_priv *pmlmepriv, int state) +{ + spin_lock_bh(&pmlmepriv->lock); + if (check_fwstate(pmlmepriv, state) == true) + pmlmepriv->fw_state ^= state; + spin_unlock_bh(&pmlmepriv->lock); +} + +static inline void clr_fwstate_ex(struct mlme_priv *pmlmepriv, int state) +{ + spin_lock_bh(&pmlmepriv->lock); + _clr_fwstate_(pmlmepriv, state); + spin_unlock_bh(&pmlmepriv->lock); +} + +u16 rtw_get_capability(struct wlan_bssid_ex *bss); +void rtw_update_scanned_network(struct adapter *adapter, + struct wlan_bssid_ex *target); +void rtw_disconnect_hdl_under_linked(struct adapter *adapter, + struct sta_info *psta, u8 free_assoc); +void rtw_generate_random_ibss(u8 *pibss); +struct wlan_network *rtw_find_network(struct __queue *scanned_queue, u8 *addr); +struct wlan_network *rtw_get_oldest_wlan_network(struct __queue *scanned_queue); + +void rtw_free_assoc_resources(struct adapter *adapter); +void rtw_free_assoc_resources_locked(struct adapter *adapter); +void rtw_indicate_disconnect(struct adapter *adapter); +void rtw_indicate_connect(struct adapter *adapter); +void rtw_indicate_scan_done(struct adapter *padapter, bool aborted); +void rtw_scan_abort(struct adapter *adapter); + +int rtw_restruct_sec_ie(struct adapter *adapter, u8 *in_ie, u8 *out_ie, + uint in_len); +int rtw_restruct_wmm_ie(struct adapter *adapter, u8 *in_ie, u8 *out_ie, + uint in_len, uint initial_out_len); +void rtw_init_registrypriv_dev_network(struct adapter *adapter); + +void rtw_update_registrypriv_dev_network(struct adapter *adapter); + +void rtw_get_encrypt_decrypt_from_registrypriv(struct adapter *adapter); + +void _rtw_join_timeout_handler(struct timer_list *t); +void rtw_scan_timeout_handler(struct timer_list *t); + +void rtw_dynamic_check_timer_handlder(struct timer_list *t); +#define rtw_is_scan_deny(adapter) false +#define rtw_clear_scan_deny(adapter) do {} while (0) +#define rtw_set_scan_deny_timer_hdl(adapter) do {} while (0) +#define rtw_set_scan_deny(adapter, ms) do {} while (0) + +void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); + +struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv); + +void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, + struct wlan_network *pnetwork); + +int rtw_if_up(struct adapter *padapter); + +u8 *rtw_get_capability_from_ie(u8 *ie); +u8 *rtw_get_beacon_interval_from_ie(u8 *ie); + +void rtw_joinbss_reset(struct adapter *padapter); + +unsigned int rtw_restructure_ht_ie(struct adapter *padapter, u8 *in_ie, + u8 *out_ie, uint in_len, uint *pout_len); +void rtw_update_ht_cap(struct adapter *padapter, u8 *pie, uint ie_len); +void rtw_issue_addbareq_cmd(struct adapter *padapter, + struct xmit_frame *pxmitframe); + +int rtw_is_same_ibss(struct adapter *adapter, struct wlan_network *pnetwork); +int is_same_network(struct wlan_bssid_ex *src, struct wlan_bssid_ex *dst); + +void rtw_roaming(struct adapter *padapter, struct wlan_network *tgt_network); +void _rtw_roaming(struct adapter *padapter, struct wlan_network *tgt_network); + +void rtw_stassoc_hw_rpt(struct adapter *adapter, struct sta_info *psta); + +#endif /* __RTL871X_MLME_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_mlme_ext.h b/drivers/staging/rtl8188eu/include/rtw_mlme_ext.h new file mode 100644 index 0000000..af323fb --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_mlme_ext.h @@ -0,0 +1,727 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_MLME_EXT_H_ +#define __RTW_MLME_EXT_H_ + +#include <osdep_service.h> +#include <drv_types.h> +#include <wlan_bssdef.h> + + +/* Commented by Albert 20101105 */ +/* Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) */ +/* The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. */ +/* So, this driver tried to extend the dwell time for each scanning channel. */ +/* This will increase the chance to receive the probe response from SoftAP. */ + +#define SURVEY_TO (100) +#define REAUTH_TO (300) /* 50) */ +#define REASSOC_TO (300) /* 50) */ +/* define DISCONNECT_TO (3000) */ +#define ADDBA_TO (2000) + +#define LINKED_TO (1) /* unit:2 sec, 1x2=2 sec */ + +#define REAUTH_LIMIT (4) +#define REASSOC_LIMIT (4) +#define READDBA_LIMIT (2) + +#define ROAMING_LIMIT 8 + +#define DYNAMIC_FUNC_DISABLE (0x0) + +/* ====== ODM_ABILITY_E ======== */ +/* BB ODM section BIT 0-15 */ +#define DYNAMIC_BB_DIG BIT(0) +#define DYNAMIC_BB_RA_MASK BIT(1) +#define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2) +#define DYNAMIC_BB_BB_FA_CNT BIT(3) + +#define DYNAMIC_BB_RSSI_MONITOR BIT(4) +#define DYNAMIC_BB_CCK_PD BIT(5) +#define DYNAMIC_BB_ANT_DIV BIT(6) +#define DYNAMIC_BB_PWR_SAVE BIT(7) +#define DYNAMIC_BB_PWR_TRA BIT(8) +#define DYNAMIC_BB_RATE_ADAPTIVE BIT(9) +#define DYNAMIC_BB_PATH_DIV BIT(10) +#define DYNAMIC_BB_PSD BIT(11) + +/* MAC DM section BIT 16-23 */ +#define DYNAMIC_MAC_EDCA_TURBO BIT(16) +#define DYNAMIC_MAC_EARLY_MODE BIT(17) + +/* RF ODM section BIT 24-31 */ +#define DYNAMIC_RF_TX_PWR_TRACK BIT(24) +#define DYNAMIC_RF_RX_GAIN_TRACK BIT(25) +#define DYNAMIC_RF_CALIBRATION BIT(26) + +#define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF + +#define _HW_STATE_NOLINK_ 0x00 +#define _HW_STATE_ADHOC_ 0x01 +#define _HW_STATE_STATION_ 0x02 +#define _HW_STATE_AP_ 0x03 + + +#define _1M_RATE_ 0 +#define _2M_RATE_ 1 +#define _5M_RATE_ 2 +#define _11M_RATE_ 3 +#define _6M_RATE_ 4 +#define _9M_RATE_ 5 +#define _12M_RATE_ 6 +#define _18M_RATE_ 7 +#define _24M_RATE_ 8 +#define _36M_RATE_ 9 +#define _48M_RATE_ 10 +#define _54M_RATE_ 11 + + +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WMM_OUI[]; +extern unsigned char WPS_OUI[]; +extern unsigned char WFD_OUI[]; +extern unsigned char P2P_OUI[]; + +extern unsigned char WMM_INFO_OUI[]; +extern unsigned char WMM_PARA_OUI[]; + +/* Channel Plan Type. */ +/* Note: */ +/* We just add new channel plan when the new channel plan is different + * from any of the following channel plan. + */ +/* If you just want to customize the actions(scan period or join actions) + * about one of the channel plan, + */ +/* customize them in struct rt_channel_info in the RT_CHANNEL_LIST. */ +enum RT_CHANNEL_DOMAIN { + /* old channel plan mapping ===== */ + RT_CHANNEL_DOMAIN_FCC = 0x00, + RT_CHANNEL_DOMAIN_IC = 0x01, + RT_CHANNEL_DOMAIN_ETSI = 0x02, + RT_CHANNEL_DOMAIN_SPAIN = 0x03, + RT_CHANNEL_DOMAIN_FRANCE = 0x04, + RT_CHANNEL_DOMAIN_MKK = 0x05, + RT_CHANNEL_DOMAIN_MKK1 = 0x06, + RT_CHANNEL_DOMAIN_ISRAEL = 0x07, + RT_CHANNEL_DOMAIN_TELEC = 0x08, + RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x09, + RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0x0A, + RT_CHANNEL_DOMAIN_TAIWAN = 0x0B, + RT_CHANNEL_DOMAIN_CHINA = 0x0C, + RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0x0D, + RT_CHANNEL_DOMAIN_KOREA = 0x0E, + RT_CHANNEL_DOMAIN_TURKEY = 0x0F, + RT_CHANNEL_DOMAIN_JAPAN = 0x10, + RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11, + RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12, + RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, + RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, + + /* new channel plan mapping, (2GDOMAIN_5GDOMAIN) ===== */ + RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, + RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, + RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, + RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23, + RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24, + RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25, + RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26, + RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27, + RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28, + RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29, + RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30, + RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31, + RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32, + RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33, + RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34, + RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35, + RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36, + RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37, + RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38, + RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, + RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, + RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G = 0x41, + /* Add new channel plan above this line=============== */ + RT_CHANNEL_DOMAIN_MAX, + RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, +}; + +enum RT_CHANNEL_DOMAIN_2G { + RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, /* Worldwide 13 */ + RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, /* Europe */ + RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, /* US */ + RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, /* Japan */ + RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, /* France */ + RT_CHANNEL_DOMAIN_2G_NULL = 0x05, + /* Add new channel plan above this line=============== */ + RT_CHANNEL_DOMAIN_2G_MAX, +}; + +#define rtw_is_channel_plan_valid(chplan) \ + (chplan < RT_CHANNEL_DOMAIN_MAX || \ + chplan == RT_CHANNEL_DOMAIN_REALTEK_DEFINE) + +struct rt_channel_plan { + unsigned char Channel[MAX_CHANNEL_NUM]; + unsigned char Len; +}; + +struct rt_channel_plan_2g { + unsigned char Channel[MAX_CHANNEL_NUM_2G]; + unsigned char Len; +}; + +struct rt_channel_plan_map { + unsigned char Index2G; +}; + +static const struct { + int channel_plan; + char *name; +} channel_table[] = { { RT_CHANNEL_DOMAIN_FCC, "US" }, + { RT_CHANNEL_DOMAIN_ETSI, "EU" }, + { RT_CHANNEL_DOMAIN_MKK, "JP" }, + { RT_CHANNEL_DOMAIN_CHINA, "CN"} }; + +enum Associated_AP { + atherosAP = 0, + broadcomAP = 1, + ciscoAP = 2, + marvellAP = 3, + ralinkAP = 4, + realtekAP = 5, + airgocapAP = 6, + unknownAP = 7, + maxAP, +}; + +enum HT_IOT_PEER { + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO = 6, + HT_IOT_PEER_MERU = 7, + HT_IOT_PEER_MARVELL = 8, + HT_IOT_PEER_REALTEK_SOFTAP = 9,/* peer is RealTek SOFT_AP */ + HT_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */ + HT_IOT_PEER_AIRGO = 11, + HT_IOT_PEER_INTEL = 12, + HT_IOT_PEER_RTK_APCLIENT = 13, + HT_IOT_PEER_REALTEK_81XX = 14, + HT_IOT_PEER_REALTEK_WOW = 15, + HT_IOT_PEER_TENDA = 16, + HT_IOT_PEER_MAX = 17 +}; + +enum SCAN_STATE { + SCAN_DISABLE = 0, + SCAN_START = 1, + SCAN_TXNULL = 2, + SCAN_PROCESS = 3, + SCAN_COMPLETE = 4, + SCAN_STATE_MAX, +}; + +struct mlme_handler { + unsigned int num; + char *str; + unsigned int (*func)(struct adapter *adapt, struct recv_frame *frame); +}; + +struct action_handler { + unsigned int num; + char *str; + unsigned int (*func)(struct adapter *adapt, struct recv_frame *frame); +}; + +struct ss_res { + int state; + int bss_cnt; + int channel_idx; + int scan_mode; + u8 ssid_num; + u8 ch_num; + struct ndis_802_11_ssid ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; +}; + +/* define AP_MODE 0x0C */ +/* define STATION_MODE 0x08 */ +/* define AD_HOC_MODE 0x04 */ +/* define NO_LINK_MODE 0x00 */ + +#define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_ +#define WIFI_FW_STATION_STATE _HW_STATE_STATION_ +#define WIFI_FW_AP_STATE _HW_STATE_AP_ +#define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_ + +#define WIFI_FW_AUTH_NULL 0x00000100 +#define WIFI_FW_AUTH_STATE 0x00000200 +#define WIFI_FW_AUTH_SUCCESS 0x00000400 + +#define WIFI_FW_ASSOC_STATE 0x00002000 +#define WIFI_FW_ASSOC_SUCCESS 0x00004000 + +#define WIFI_FW_LINKING_STATE (WIFI_FW_AUTH_NULL | \ + WIFI_FW_AUTH_STATE | \ + WIFI_FW_AUTH_SUCCESS | \ + WIFI_FW_ASSOC_STATE) + +struct FW_Sta_Info { + struct sta_info *psta; + u32 status; + u32 rx_pkt; + u32 retry; + unsigned char SupportedRates[NDIS_802_11_LENGTH_RATES_EX]; +}; + +/* + * Usage: + * When one iface acted as AP mode and the other iface is STA mode and scanning, + * it should switch back to AP's operating channel periodically. + * Parameters info: + * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to + * AP's operating channel for + * RTW_STAY_AP_CH_MILLISECOND * SURVEY_TO milliseconds. + * Example: + * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1, + * RTW_SCAN_NUM_OF_CH is 8, RTW_STAY_AP_CH_MS is 3 and SURVEY_TO is 100. + * When it's STA mode gets set_scan command, + * it would + * 1. Doing the scan on channel 1.2.3.4.5.6.7.8 + * 2. Back to channel 1 for 300 milliseconds + * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52 + * 4. Back to channel 1 for 300 milliseconds + * 5. ... and so on, till survey done. + */ + +struct mlme_ext_info { + u32 state; + u32 reauth_count; + u32 reassoc_count; + u32 link_count; + u32 auth_seq; + u32 auth_algo; /* 802.11 auth, could be open, shared, auto */ + u32 authModeToggle; + u32 enc_algo;/* encrypt algorithm; */ + u32 key_index; /* this is only valid for legacy wep, + * 0~3 for key id. + */ + u32 iv; + u8 chg_txt[128]; + u16 aid; + u16 bcn_interval; + u16 capability; + u8 assoc_AP_vendor; + u8 slotTime; + u8 preamble_mode; + u8 WMM_enable; + u8 ERP_enable; + u8 ERP_IE; + u8 HT_enable; + u8 HT_caps_enable; + u8 HT_info_enable; + u8 HT_protection; + u8 turboMode_cts2self; + u8 turboMode_rtsen; + u8 SM_PS; + u8 agg_enable_bitmap; + u8 ADDBA_retry_count; + u8 candidate_tid_bitmap; + u8 dialogToken; + /* Accept ADDBA Request */ + bool accept_addba_req; + u8 bwmode_updated; + u8 hidden_ssid_mode; + + struct ADDBA_request ADDBA_req; + struct WMM_para_element WMM_param; + struct ieee80211_ht_cap HT_caps; + struct HT_info_element HT_info; + struct wlan_bssid_ex network;/* join network or bss_network, + * if in ap mode, it is the same + * as cur_network.network + */ + struct FW_Sta_Info FW_sta_info[NUM_STA]; +}; + +/* The channel information about this channel including joining, + * scanning, and power constraints. + */ +struct rt_channel_info { + u8 ChannelNum; /* The channel number. */ + enum rt_scan_type ScanType; /* Scan type such as passive + * or active scan. + */ + u32 rx_count; +}; + +int rtw_ch_set_search_ch(struct rt_channel_info *ch_set, const u32 ch); + +/* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */ +#define P2P_MAX_REG_CLASSES 10 + +/* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of chan per regulatory class */ +#define P2P_MAX_REG_CLASS_CHANNELS 20 + +/* struct p2p_channels - List of supported channels */ +struct p2p_channels { + /* struct p2p_reg_class - Supported regulatory class */ + struct p2p_reg_class { + /* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */ + u8 reg_class; + + /* channel - Supported channels */ + u8 channel[P2P_MAX_REG_CLASS_CHANNELS]; + + /* channels - Number of channel entries in use */ + size_t channels; + } reg_class[P2P_MAX_REG_CLASSES]; + + /* reg_classes - Number of reg_class entries in use */ + size_t reg_classes; +}; + +struct p2p_oper_class_map { + enum hw_mode {IEEE80211G} mode; + u8 op_class; + u8 min_chan; + u8 max_chan; + u8 inc; + enum {BW20, BW40PLUS, BW40MINUS} bw; +}; + +struct mlme_ext_priv { + struct adapter *padapter; + u8 mlmeext_init; + atomic_t event_seq; + u16 mgnt_seq; + + unsigned char cur_channel; + unsigned char cur_bwmode; + unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */ + unsigned char cur_wireless_mode; /* NETWORK_TYPE */ + + unsigned char oper_channel; /* saved chan info when call + * set_channel_bw + */ + unsigned char oper_bwmode; + unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */ + + unsigned char max_chan_nums; + struct rt_channel_info channel_set[MAX_CHANNEL_NUM]; + struct p2p_channels channel_list; + unsigned char basicrate[NumRates]; + unsigned char datarate[NumRates]; + + struct ss_res sitesurvey_res; + struct mlme_ext_info mlmext_info;/* for sta/adhoc mode, including + * current scan/connecting/connected + * related info. For ap mode, + * network includes ap's cap_info + */ + struct timer_list survey_timer; + struct timer_list link_timer; + u16 chan_scan_time; + + u8 scan_abort; + u8 tx_rate; /* TXRATE when USERATE is set. */ + + u32 retry; /* retry for issue probereq */ + + u64 TSFValue; + +#ifdef CPTCFG_88EU_AP_MODE + unsigned char bstart_bss; +#endif + u8 update_channel_plan_by_ap_done; + /* recv_decache check for Action_public frame */ + u8 action_public_dialog_token; + u16 action_public_rxseq; + u8 active_keep_alive_check; +}; + +int init_mlme_ext_priv(struct adapter *adapter); +int init_hw_mlme_ext(struct adapter *padapter); +void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext); +void init_mlme_ext_timer(struct adapter *padapter); +void init_addba_retry_timer(struct adapter *adapt, struct sta_info *sta); +struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); + +unsigned char networktype_to_raid(unsigned char network_type); +u8 judge_network_type(struct adapter *padapter, unsigned char *rate, int len); +void get_rate_set(struct adapter *padapter, unsigned char *pbssrate, int *len); +void UpdateBrateTbl(struct adapter *padapter, u8 *mBratesOS); +void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen); + +void Save_DM_Func_Flag(struct adapter *padapter); +void Restore_DM_Func_Flag(struct adapter *padapter); +void Switch_DM_Func(struct adapter *padapter, u32 mode, u8 enable); + +void Set_MSR(struct adapter *padapter, u8 type); + +u8 rtw_get_oper_ch(struct adapter *adapter); +void rtw_set_oper_ch(struct adapter *adapter, u8 ch); +void rtw_set_oper_bw(struct adapter *adapter, u8 bw); +void rtw_set_oper_choffset(struct adapter *adapter, u8 offset); + +void set_channel_bwmode(struct adapter *padapter, unsigned char channel, + unsigned char channel_offset, unsigned short bwmode); +void SelectChannel(struct adapter *padapter, unsigned char channel); +void SetBWMode(struct adapter *padapter, unsigned short bwmode, + unsigned char channel_offset); + +unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval); + +void write_cam(struct adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_entry(struct adapter *padapter, u8 entry); + +void invalidate_cam_all(struct adapter *padapter); + +int allocate_fw_sta_entry(struct adapter *padapter); +void flush_all_cam_entry(struct adapter *padapter); + +void update_network(struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src, + struct adapter *adapter, bool update_ie); + +int get_bsstype(unsigned short capability); +u16 get_beacon_interval(struct wlan_bssid_ex *bss); + +int is_client_associated_to_ap(struct adapter *padapter); +int is_client_associated_to_ibss(struct adapter *padapter); +int is_IBSS_empty(struct adapter *padapter); + +unsigned char check_assoc_AP(u8 *pframe, uint len); + +int WMM_param_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE); +void WMMOnAssocRsp(struct adapter *padapter); + +void HT_caps_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE); +void HT_info_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE); +void HTOnAssocRsp(struct adapter *padapter); + +void ERP_IE_handler(struct adapter *padapter, struct ndis_802_11_var_ie *pIE); +void VCS_update(struct adapter *padapter, struct sta_info *psta); + +void update_beacon_info(struct adapter *padapter, u8 *pframe, uint len, + struct sta_info *psta); +int rtw_check_bcn_info(struct adapter *Adapter, u8 *pframe, u32 packet_len); +void update_IOT_info(struct adapter *padapter); +void update_capinfo(struct adapter *adapter, u16 updatecap); +void update_wireless_mode(struct adapter *padapter); +void update_tx_basic_rate(struct adapter *padapter, u8 modulation); +void update_bmc_sta_support_rate(struct adapter *padapter, u32 mac_id); +int update_sta_support_rate(struct adapter *padapter, u8 *pvar_ie, + uint var_ie_len, int cam_idx); + +/* for sta/adhoc mode */ +void update_sta_info(struct adapter *padapter, struct sta_info *psta); +unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz); +unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz); +unsigned int update_MSC_rate(struct ieee80211_ht_cap *pHT_caps); +void Update_RA_Entry(struct adapter *padapter, u32 mac_id); +void set_sta_rate(struct adapter *padapter, struct sta_info *psta); + +unsigned char get_highest_rate_idx(u32 mask); +int support_short_GI(struct adapter *padapter, struct ieee80211_ht_cap *caps); +unsigned int is_ap_in_tkip(struct adapter *padapter); +unsigned int is_ap_in_wep(struct adapter *padapter); + +void report_join_res(struct adapter *padapter, int res); +void report_survey_event(struct adapter *padapter, + struct recv_frame *precv_frame); +void report_surveydone_event(struct adapter *padapter); +void report_del_sta_event(struct adapter *padapter, + unsigned char *addr, unsigned short reason); +void report_add_sta_event(struct adapter *padapter, unsigned char *addr, + int cam_idx); + +void beacon_timing_control(struct adapter *padapter); +u8 set_tx_beacon_cmd(struct adapter *padapter); +unsigned int setup_beacon_frame(struct adapter *padapter, + unsigned char *beacon_frame); +void update_mgnt_tx_rate(struct adapter *padapter, u8 rate); +void update_mgntframe_attrib(struct adapter *padapter, + struct pkt_attrib *pattrib); + +int issue_nulldata(struct adapter *padapter, unsigned char *da, + unsigned int power_mode, int try_cnt, int wait_ms); +int issue_qos_nulldata(struct adapter *padapter, unsigned char *da, + u16 tid, int try_cnt, int wait_ms); +int issue_deauth(struct adapter *padapter, unsigned char *da, + unsigned short reason); +unsigned int send_delba(struct adapter *padapter, u8 initiator, u8 *addr); +unsigned int send_beacon(struct adapter *padapter); + +void mlmeext_joinbss_event_callback(struct adapter *padapter, int join_res); +void mlmeext_sta_del_event_callback(struct adapter *padapter); +void mlmeext_sta_add_event_callback(struct adapter *padapter, + struct sta_info *psta); + +void linked_status_chk(struct adapter *padapter); + +void survey_timer_hdl(struct timer_list *t); +void link_timer_hdl(struct timer_list *t); +void addba_timer_hdl(struct timer_list *t); + +#define set_survey_timer(mlmeext, ms) \ + mod_timer(&mlmeext->survey_timer, jiffies + \ + msecs_to_jiffies(ms)) + +#define set_link_timer(mlmeext, ms) \ + mod_timer(&mlmeext->link_timer, jiffies + \ + msecs_to_jiffies(ms)) + +int cckrates_included(unsigned char *rate, int ratelen); +int cckratesonly_included(unsigned char *rate, int ratelen); + +void process_addba_req(struct adapter *padapter, u8 *paddba_req, u8 *addr); + +void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); +void correct_TSF(struct adapter *padapter, struct mlme_ext_priv *pmlmeext); + +struct cmd_hdl { + uint parmsize; + u8 (*h2cfuns)(struct adapter *padapter, u8 *pbuf); +}; + +u8 read_macreg_hdl(struct adapter *padapter, u8 *pbuf); +u8 write_macreg_hdl(struct adapter *padapter, u8 *pbuf); +u8 read_bbreg_hdl(struct adapter *padapter, u8 *pbuf); +u8 write_bbreg_hdl(struct adapter *padapter, u8 *pbuf); +u8 read_rfreg_hdl(struct adapter *padapter, u8 *pbuf); +u8 write_rfreg_hdl(struct adapter *padapter, u8 *pbuf); +u8 join_cmd_hdl(struct adapter *padapter, u8 *pbuf); +u8 disconnect_hdl(struct adapter *padapter, u8 *pbuf); +u8 createbss_hdl(struct adapter *padapter, u8 *pbuf); +u8 setopmode_hdl(struct adapter *padapter, u8 *pbuf); +u8 sitesurvey_cmd_hdl(struct adapter *padapter, u8 *pbuf); +u8 setauth_hdl(struct adapter *padapter, u8 *pbuf); +u8 setkey_hdl(struct adapter *padapter, u8 *pbuf); +u8 set_stakey_hdl(struct adapter *padapter, u8 *pbuf); +u8 set_assocsta_hdl(struct adapter *padapter, u8 *pbuf); +u8 del_assocsta_hdl(struct adapter *padapter, u8 *pbuf); +u8 add_ba_hdl(struct adapter *padapter, unsigned char *pbuf); + +u8 mlme_evt_hdl(struct adapter *padapter, unsigned char *pbuf); +u8 h2c_msg_hdl(struct adapter *padapter, unsigned char *pbuf); +u8 tx_beacon_hdl(struct adapter *padapter, unsigned char *pbuf); +u8 set_ch_hdl(struct adapter *padapter, u8 *pbuf); +u8 set_chplan_hdl(struct adapter *padapter, unsigned char *pbuf); +u8 led_blink_hdl(struct adapter *padapter, unsigned char *pbuf); +/* Handling DFS channel switch announcement ie. */ +u8 set_csa_hdl(struct adapter *padapter, unsigned char *pbuf); +u8 tdls_hdl(struct adapter *padapter, unsigned char *pbuf); + +#ifdef _RTW_CMD_C_ + +static struct cmd_hdl wlancmds[] = { + {sizeof(struct wlan_bssid_ex), join_cmd_hdl}, + {sizeof(struct disconnect_parm), disconnect_hdl}, + {sizeof(struct wlan_bssid_ex), createbss_hdl}, + {sizeof(struct setopmode_parm), setopmode_hdl}, + {sizeof(struct sitesurvey_parm), sitesurvey_cmd_hdl}, + {sizeof(struct setauth_parm), setauth_hdl}, + {sizeof(struct setkey_parm), setkey_hdl}, + {sizeof(struct set_stakey_parm), set_stakey_hdl}, + {sizeof(struct set_assocsta_parm), NULL}, + {sizeof(struct addBaReq_parm), add_ba_hdl}, + {sizeof(struct set_ch_parm), set_ch_hdl}, + {sizeof(struct wlan_bssid_ex), tx_beacon_hdl}, + {0, mlme_evt_hdl}, + {0, rtw_drvextra_cmd_hdl}, + {sizeof(struct SetChannelPlan_param), set_chplan_hdl} +}; + +#endif + +struct C2HEvent_Header { +#ifdef __LITTLE_ENDIAN + unsigned int len:16; + unsigned int ID:8; + unsigned int seq:8; +#elif defined(__BIG_ENDIAN) + unsigned int seq:8; + unsigned int ID:8; + unsigned int len:16; +#endif + unsigned int rsvd; +}; + +void rtw_dummy_event_callback(struct adapter *adapter, u8 *pbuf); +void rtw_fwdbg_event_callback(struct adapter *adapter, u8 *pbuf); + +enum rtw_c2h_event { + _Read_MACREG_EVT_ = 0, /*0*/ + _Read_BBREG_EVT_, + _Read_RFREG_EVT_, + _Read_EEPROM_EVT_, + _Read_EFUSE_EVT_, + _Read_CAM_EVT_, /*5*/ + _Get_BasicRate_EVT_, + _Get_DataRate_EVT_, + _Survey_EVT_, /*8*/ + _SurveyDone_EVT_, /*9*/ + + _JoinBss_EVT_, /*10*/ + _AddSTA_EVT_, + _DelSTA_EVT_, + _AtimDone_EVT_, + _TX_Report_EVT_, + _CCX_Report_EVT_, /*15*/ + _DTM_Report_EVT_, + _TX_Rate_Statistics_EVT_, + _C2HLBK_EVT_, + _FWDBG_EVT_, + _C2HFEEDBACK_EVT_, /*20*/ + _ADDBA_EVT_, + _C2HBCN_EVT_, + _ReportPwrState_EVT_, /* filen: only for PCIE, USB */ + _CloseRF_EVT_, /* filen: only for PCIE, + * work around ASPM + */ + MAX_C2HEVT +}; + + +#ifdef _RTW_MLME_EXT_C_ + +static struct fwevent wlanevents[] = { + {0, rtw_dummy_event_callback}, /*0*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, &rtw_survey_event_callback}, /*8*/ + {sizeof(struct surveydone_event), &rtw_surveydone_event_callback},/*9*/ + {0, &rtw_joinbss_event_callback}, /*10*/ + {sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, + {sizeof(struct stadel_event), &rtw_stadel_event_callback}, + {0, &rtw_atimdone_event_callback}, + {0, rtw_dummy_event_callback}, + {0, NULL}, /*15*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, rtw_fwdbg_event_callback}, + {0, NULL}, /*20*/ + {0, NULL}, + {0, NULL}, + {0, &rtw_cpwm_event_callback}, + {0, NULL}, +}; + +#endif/* _RTL_MLME_EXT_C_ */ + +#endif /* __RTW_MLME_EXT_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_pwrctrl.h b/drivers/staging/rtl8188eu/include/rtw_pwrctrl.h new file mode 100644 index 0000000..4046349 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_pwrctrl.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_PWRCTRL_H_ +#define __RTW_PWRCTRL_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +#define FW_PWR0 0 +#define FW_PWR1 1 +#define FW_PWR2 2 +#define FW_PWR3 3 +#define HW_PWR0 7 +#define HW_PWR1 6 +#define HW_PWR2 2 +#define HW_PWR3 0 +#define HW_PWR4 8 + +#define FW_PWRMSK 0x7 + +#define XMIT_ALIVE BIT(0) +#define RECV_ALIVE BIT(1) +#define CMD_ALIVE BIT(2) +#define EVT_ALIVE BIT(3) + +enum power_mgnt { + PS_MODE_ACTIVE = 0, + PS_MODE_MIN, + PS_MODE_MAX, + PS_MODE_DTIM, + PS_MODE_VOIP, + PS_MODE_UAPSD_WMM, + PS_MODE_UAPSD, + PS_MODE_IBSS, + PS_MODE_WWLAN, + PM_Radio_Off, + PM_Card_Disable, + PS_MODE_NUM +}; + +/* + * BIT[2:0] = HW state + * BIT[3] = Protocol PS state, 0: register active state, + * 1: register sleep state + * BIT[4] = sub-state + */ + +#define PS_DPS BIT(0) +#define PS_LCLK (PS_DPS) +#define PS_RF_OFF BIT(1) +#define PS_ALL_ON BIT(2) +#define PS_ST_ACTIVE BIT(3) + +#define PS_ISR_ENABLE BIT(4) +#define PS_IMR_ENABLE BIT(5) +#define PS_ACK BIT(6) +#define PS_TOGGLE BIT(7) + +#define PS_STATE_MASK (0x0F) +#define PS_STATE_HW_MASK (0x07) +#define PS_SEQ_MASK (0xc0) + +#define PS_STATE(x) (PS_STATE_MASK & (x)) +#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) +#define PS_SEQ(x) (PS_SEQ_MASK & (x)) + +#define PS_STATE_S0 (PS_DPS) +#define PS_STATE_S1 (PS_LCLK) +#define PS_STATE_S2 (PS_RF_OFF) +#define PS_STATE_S3 (PS_ALL_ON) +#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) + +#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) +#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) +#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) + +struct reportpwrstate_parm { + unsigned char mode; + unsigned char state; /* the CPWM value */ + unsigned short rsvd; +}; + +#define LPS_DELAY_TIME 1*HZ /* 1 sec */ + +#define EXE_PWR_NONE 0x01 +#define EXE_PWR_IPS 0x02 +#define EXE_PWR_LPS 0x04 + +/* RF state. */ +enum rt_rf_power_state { + rf_on, /* RF is on after RFSleep or RFOff */ + rf_sleep, /* 802.11 Power Save mode */ + rf_off, /* HW/SW Radio OFF or Inactive Power Save */ + /* Add the new RF state above this line===== */ + rf_max +}; + +/* RF Off Level for IPS or HW/SW radio off */ +#define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */ +#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */ +#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */ +#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-init hw param*/ +#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW*/ +#define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */ +#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock + * Req in initialization. + */ +#define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R + * if no packet is RX or TX. + */ +#define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */ + +#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) \ + ((ppsc->cur_ps_level & _PS_FLAG) ? true : false) +#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) \ + (ppsc->cur_ps_level &= (~(_PS_FLAG))) +#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) \ + (ppsc->cur_ps_level |= _PS_FLAG) + +enum _PS_BBRegBackup_ { + PSBBREG_RF0 = 0, + PSBBREG_RF1, + PSBBREG_RF2, + PSBBREG_AFE0, + PSBBREG_TOTALCNT +}; + +enum { /* for ips_mode */ + IPS_NONE = 0, + IPS_NORMAL, + IPS_LEVEL_2, +}; + +struct pwrctrl_priv { + struct mutex mutex_lock; + volatile u8 rpwm; /* requested power state for fw */ + volatile u8 cpwm; /* fw current power state. updated when + * 1. read from HCPWM 2. driver lowers power level + */ + volatile u8 tog; /* toggling */ + volatile u8 cpwm_tog; /* toggling */ + + u8 pwr_mode; + u8 smart_ps; + u8 bcn_ant_mode; + + u32 alives; + struct work_struct cpwm_event; + u8 bpower_saving; + + u8 b_hw_radio_off; + u8 reg_rfoff; + u8 reg_pdnmode; /* powerdown mode */ + u32 rfoff_reason; + + /* RF OFF Level */ + u32 cur_ps_level; + u32 reg_rfps_level; + uint ips_enter_cnts; + uint ips_leave_cnts; + + u8 ips_mode; + u8 ips_mode_req; /* used to accept the mode setting request, + * will update to ipsmode later + */ + uint bips_processing; + unsigned long ips_deny_time; /* will deny IPS when system time less than this */ + u8 ps_processing; /* temp used to mark whether in rtw_ps_processor */ + + u8 bLeisurePs; + u8 LpsIdleCount; + u8 power_mgnt; + u8 bFwCurrentInPSMode; + u32 DelayLPSLastTimeStamp; + u8 btcoex_rfon; + s32 pnp_current_pwr_state; + u8 pnp_bstop_trx; + + u8 bInternalAutoSuspend; + u8 bInSuspend; + u8 bSupportRemoteWakeup; + struct timer_list pwr_state_check_timer; + int pwr_state_check_interval; + u8 pwr_state_check_cnts; + + int ps_flag; + + enum rt_rf_power_state rf_pwrstate;/* cur power state */ + enum rt_rf_power_state change_rfpwrstate; + + u8 wepkeymask; + u8 bHWPowerdown;/* if support hw power down */ + u8 bHWPwrPindetect; + u8 bkeepfwalive; + u8 brfoffbyhw; + unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; +}; + +#define rtw_get_ips_mode_req(pwrctrlpriv) \ + (pwrctrlpriv)->ips_mode_req + +#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \ + ((pwrctrlpriv)->ips_mode_req = (ips_mode)) + +#define RTW_PWR_STATE_CHK_INTERVAL 2000 + +#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \ + mod_timer(&pwrctrlpriv->pwr_state_check_timer, \ + jiffies + msecs_to_jiffies(ms)) + +#define rtw_set_pwr_state_check_timer(pwrctrl) \ + _rtw_set_pwr_state_check_timer((pwrctrl), \ + (pwrctrl)->pwr_state_check_interval) + +void rtw_init_pwrctrl_priv(struct adapter *adapter); + +void rtw_set_ps_mode(struct adapter *adapter, u8 ps_mode, u8 smart_ps, + u8 bcn_ant_mode); +void rtw_set_rpwm(struct adapter *adapter, u8 val8); +void LeaveAllPowerSaveMode(struct adapter *adapter); +void ips_enter(struct adapter *padapter); +int ips_leave(struct adapter *padapter); + +void rtw_ps_processor(struct adapter *padapter); + +enum rt_rf_power_state RfOnOffDetect(struct adapter *iadapter); + +s32 LPS_RF_ON_check(struct adapter *adapter, u32 delay_ms); +void LPS_Enter(struct adapter *adapter); +void LPS_Leave(struct adapter *adapter); + +int _rtw_pwr_wakeup(struct adapter *adapter, u32 ips_defer_ms, + const char *caller); +#define rtw_pwr_wakeup(adapter) \ + _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __func__) +#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) \ + _rtw_pwr_wakeup(adapter, ips_deffer_ms, __func__) +int rtw_pm_set_ips(struct adapter *adapter, u8 mode); +int rtw_pm_set_lps(struct adapter *adapter, u8 mode); + +#endif /* __RTL871X_PWRCTRL_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_qos.h b/drivers/staging/rtl8188eu/include/rtw_qos.h new file mode 100644 index 0000000..bf617da --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_qos.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _RTW_QOS_H_ +#define _RTW_QOS_H_ + +#include <osdep_service.h> + +struct qos_priv { + unsigned int qos_option; /* bit mask option: u-apsd, + * s-apsd, ts, block ack... + */ +}; + +#endif /* _RTL871X_QOS_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_recv.h b/drivers/staging/rtl8188eu/include/rtw_recv.h new file mode 100644 index 0000000..54b7ba3 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_recv.h @@ -0,0 +1,264 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _RTW_RECV_H_ +#define _RTW_RECV_H_ + +#include <osdep_service.h> +#include <drv_types.h> + + +#define NR_RECVFRAME 256 + +#define RXFRAME_ALIGN 8 +#define RXFRAME_ALIGN_SZ (1<<RXFRAME_ALIGN) + +#define MAX_RXFRAME_CNT 512 +#define MAX_RX_NUMBLKS (32) +#define RECVFRAME_HDR_ALIGN 128 + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define MAX_SUBFRAME_COUNT 64 + +/* for Rx reordering buffer control */ +struct recv_reorder_ctrl { + struct adapter *padapter; + u8 enable; + u16 indicate_seq;/* wstart_b, init_value=0xffff */ + u16 wend_b; + u8 wsize_b; + struct __queue pending_recvframe_queue; + struct timer_list reordering_ctrl_timer; +}; + +struct stainfo_rxcache { + u16 tid_rxseq[16]; +/* + * unsigned short tid0_rxseq; + * unsigned short tid1_rxseq; + * unsigned short tid2_rxseq; + * unsigned short tid3_rxseq; + * unsigned short tid4_rxseq; + * unsigned short tid5_rxseq; + * unsigned short tid6_rxseq; + * unsigned short tid7_rxseq; + * unsigned short tid8_rxseq; + * unsigned short tid9_rxseq; + * unsigned short tid10_rxseq; + * unsigned short tid11_rxseq; + * unsigned short tid12_rxseq; + * unsigned short tid13_rxseq; + * unsigned short tid14_rxseq; + * unsigned short tid15_rxseq; + */ +}; + +struct signal_stat { + u8 update_req; /* used to indicate */ + u8 avg_val; /* avg of valid elements */ + u32 total_num; /* num of valid elements */ + u32 total_val; /* sum of valid elements */ +}; +#define MAX_PATH_NUM_92CS 3 +struct phy_info { + u8 RxPWDBAll; + u8 SignalQuality; /* in 0-100 index. */ + u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ + u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ + s8 RxPower; /* in dBm Translate from PWdB */ +/* Real power in dBm for this packet, no beautification and aggregation. + * Keep this raw info to be used for the other procedures. + */ + s8 recvpower; + u8 BTRxRSSIPercentage; + u8 SignalStrength; /* in 0-100 index. */ + u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ + u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ +}; + +struct rx_pkt_attrib { + u16 pkt_len; + u8 physt; + u8 drvinfo_sz; + u8 shift_sz; + u8 hdrlen; /* the WLAN Header Len */ + u8 to_fr_ds; + u8 amsdu; + u8 qos; + u8 priority; + u8 pw_save; + u8 mdata; + u16 seq_num; + u8 frag_num; + u8 mfrag; + u8 order; + u8 privacy; /* in frame_ctrl field */ + u8 bdecrypted; + u8 encrypt; /* when 0 indicate no encrypt. when non-zero, + * indicate the encrypt algorithm + */ + u8 iv_len; + u8 icv_len; + u8 crc_err; + u8 icv_err; + + u16 eth_type; + + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + u8 bssid[ETH_ALEN]; + + u8 ack_policy; + + u8 key_index; + + u8 mcs_rate; + u8 rxht; + u8 sgi; + u8 pkt_rpt_type; + u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */ + + struct phy_info phy_info; +}; + + +/* These definition is used for Rx packet reordering. */ +#define SN_LESS(a, b) (((a - b) & 0x800) != 0) +#define SN_EQUAL(a, b) (a == b) +#define REORDER_WAIT_TIME (50) /* (ms) */ + +#define RXDESC_SIZE 24 +#define RXDESC_OFFSET RXDESC_SIZE + +struct recv_stat { + __le32 rxdw0; + __le32 rxdw1; + __le32 rxdw2; + __le32 rxdw3; + __le32 rxdw4; + __le32 rxdw5; +}; + +/* + * accesser of recv_priv: rtw_recv_entry(dispatch / passive level); + * recv_thread(passive) ; returnpkt(dispatch) + * ; halt(passive) ; + * + * using enter_critical section to protect + */ +struct recv_priv { + struct __queue free_recv_queue; + struct __queue recv_pending_queue; + struct __queue uc_swdec_pending_queue; + void *pallocated_frame_buf; + struct adapter *adapter; + u32 bIsAnyNonBEPkts; + u64 rx_bytes; + u64 rx_pkts; + u64 rx_drop; + u64 last_rx_bytes; + + struct tasklet_struct irq_prepare_beacon_tasklet; + struct tasklet_struct recv_tasklet; + struct sk_buff_head free_recv_skb_queue; + struct sk_buff_head rx_skb_queue; + struct recv_buf *precv_buf; /* 4 alignment */ + struct __queue free_recv_buf_queue; + /* For display the phy information */ + s8 rssi; + s8 rxpwdb; + u8 signal_strength; + u8 signal_qual; + u8 noise; + s8 RxRssi[2]; + + struct timer_list signal_stat_timer; + u32 signal_stat_sampling_interval; + struct signal_stat signal_qual_data; + struct signal_stat signal_strength_data; +}; + +#define rtw_set_signal_stat_timer(recvpriv) \ + mod_timer(&(recvpriv)->signal_stat_timer, jiffies + \ + msecs_to_jiffies((recvpriv)->signal_stat_sampling_interval)) + +struct sta_recv_priv { + spinlock_t lock; + int option; + struct __queue defrag_q; /* keeping the fragment frame until defrag */ + struct stainfo_rxcache rxcache; +}; + +struct recv_buf { + struct adapter *adapter; + struct urb *purb; + struct sk_buff *pskb; + u8 reuse; +}; + +/* + * head -----> + * + * data -----> + * + * payload + * + * tail -----> + * + * + * end -----> + * + * len = (unsigned int )(tail - data); + * + */ +struct recv_frame { + struct list_head list; + struct sk_buff *pkt; + struct adapter *adapter; + struct rx_pkt_attrib attrib; + struct sta_info *psta; + /* for A-MPDU Rx reordering buffer control */ + struct recv_reorder_ctrl *preorder_ctrl; +}; + +struct recv_frame *_rtw_alloc_recvframe(struct __queue *pfree_recv_queue); +struct recv_frame *rtw_alloc_recvframe(struct __queue *pfree_recv_queue); +void rtw_init_recvframe(struct recv_frame *precvframe, + struct recv_priv *precvpriv); +int rtw_free_recvframe(struct recv_frame *precvframe, + struct __queue *pfree_recv_queue); +#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue) +int _rtw_enqueue_recvframe(struct recv_frame *precvframe, + struct __queue *queue); +int rtw_enqueue_recvframe(struct recv_frame *precvframe, struct __queue *queue); +void rtw_free_recvframe_queue(struct __queue *pframequeue, + struct __queue *pfree_recv_queue); +u32 rtw_free_uc_swdec_pending_queue(struct adapter *adapter); + +void rtw_reordering_ctrl_timeout_handler(struct timer_list *t); + +static inline s32 translate_percentage_to_dbm(u32 sig_stren_index) +{ + s32 power; /* in dBm. */ + + /* Translate to dBm (x=0.5y-95). */ + power = (s32)((sig_stren_index + 1) >> 1); + power -= 95; + + return power; +} + + +struct sta_info; + +void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); + +void mgt_dispatcher(struct adapter *padapter, struct recv_frame *precv_frame); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtw_rf.h b/drivers/staging/rtl8188eu/include/rtw_rf.h new file mode 100644 index 0000000..b5dfb22 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_rf.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_RF_H_ +#define __RTW_RF_H_ + +#include <rtw_cmd.h> + +#define OFDM_PHY 1 +#define MIXED_PHY 2 +#define CCK_PHY 3 + +#define NumRates (13) + +/* slot time for 11g */ +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + +#define RTL8711_RF_MAX_SENS 6 +#define RTL8711_RF_DEF_SENS 4 + +/* We now define the following channels as the max channels in each + * channel plan. + */ +/* 2G, total 14 chnls */ +/* {1,2,3,4,5,6,7,8,9,10,11,12,13,14} */ +#define MAX_CHANNEL_NUM_2G 14 +#define MAX_CHANNEL_NUM 14 /* 2.4 GHz only */ + +#define NUM_REGULATORYS 1 + +/* Country codes */ +#define USA 0x555320 +#define EUROPE 0x1 /* temp, should be provided later */ +#define JAPAN 0x2 /* temp, should be provided later */ + +struct regulatory_class { + u32 starting_freq; /* MHz, */ + u8 channel_set[MAX_CHANNEL_NUM]; + u8 channel_cck_power[MAX_CHANNEL_NUM]; /* dbm */ + u8 channel_ofdm_power[MAX_CHANNEL_NUM]; /* dbm */ + u8 txpower_limit; /* dbm */ + u8 channel_spacing; /* MHz */ + u8 modem; +}; + +enum capability { + cESS = 0x0001, + cIBSS = 0x0002, + cPollable = 0x0004, + cPollReq = 0x0008, + cPrivacy = 0x0010, + cShortPreamble = 0x0020, + cPBCC = 0x0040, + cChannelAgility = 0x0080, + cSpectrumMgnt = 0x0100, + cQos = 0x0200, /* For HCCA, use with CF-Pollable + * and CF-PollReq + */ + cShortSlotTime = 0x0400, + cAPSD = 0x0800, + cRM = 0x1000, /* RRM (Radio Request Measurement) */ + cDSSS_OFDM = 0x2000, + cDelayedBA = 0x4000, + cImmediateBA = 0x8000, +}; + +enum _REG_PREAMBLE_MODE { + PREAMBLE_LONG = 1, + PREAMBLE_AUTO = 2, + PREAMBLE_SHORT = 3, +}; + +enum _RTL8712_RF_MIMO_CONFIG_ { + RTL8712_RFCONFIG_1T = 0x10, + RTL8712_RFCONFIG_2T = 0x20, + RTL8712_RFCONFIG_1R = 0x01, + RTL8712_RFCONFIG_2R = 0x02, + RTL8712_RFCONFIG_1T1R = 0x11, + RTL8712_RFCONFIG_1T2R = 0x12, + RTL8712_RFCONFIG_TURBO = 0x92, + RTL8712_RFCONFIG_2T2R = 0x22 +}; + +enum rf90_radio_path { + RF90_PATH_A = 0, /* Radio Path A */ + RF90_PATH_B = 1, /* Radio Path B */ + RF90_PATH_C = 2, /* Radio Path C */ + RF90_PATH_D = 3 /* Radio Path D */ +}; + +/* Bandwidth Offset */ +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + +/* Represent Channel Width in HT Capabilities */ +/* */ +enum ht_channel_width { + HT_CHANNEL_WIDTH_20 = 0, + HT_CHANNEL_WIDTH_40 = 1, + HT_CHANNEL_WIDTH_80 = 2, + HT_CHANNEL_WIDTH_160 = 3, + HT_CHANNEL_WIDTH_10 = 4, +}; + +/* */ +/* Represent Extension Channel Offset in HT Capabilities */ +/* This is available only in 40Mhz mode. */ +/* */ +enum ht_extchnl_offset { + HT_EXTCHNL_OFFSET_NO_EXT = 0, + HT_EXTCHNL_OFFSET_UPPER = 1, + HT_EXTCHNL_OFFSET_NO_DEF = 2, + HT_EXTCHNL_OFFSET_LOWER = 3, +}; + +/* 2007/11/15 MH Define different RF type. */ +enum rt_rf_type_def { + RF_1T2R = 0, + RF_2T4R = 1, + RF_2T2R = 2, + RF_1T1R = 3, + RF_2T2R_GREEN = 4, + RF_819X_MAX_TYPE = 5, +}; + +u32 rtw_ch2freq(u32 ch); + + +#endif /* _RTL8711_RF_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_security.h b/drivers/staging/rtl8188eu/include/rtw_security.h new file mode 100644 index 0000000..9e4ef7a --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_security.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __RTW_SECURITY_H_ +#define __RTW_SECURITY_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +#define _NO_PRIVACY_ 0x0 +#define _WEP40_ 0x1 +#define _TKIP_ 0x2 +#define _TKIP_WTMIC_ 0x3 +#define _AES_ 0x4 +#define _WEP104_ 0x5 +#define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ +#define _SMS4_ 0x06 + +#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) + +#define _WPA_IE_ID_ 0xdd +#define _WPA2_IE_ID_ 0x30 + +#define SHA256_MAC_LEN 32 +#define AES_BLOCK_SIZE 16 +#define AES_PRIV_SIZE (4 * 44) + +enum { + ENCRYP_PROTOCOL_OPENSYS, /* open system */ + ENCRYP_PROTOCOL_WEP, /* WEP */ + ENCRYP_PROTOCOL_WPA, /* WPA */ + ENCRYP_PROTOCOL_WPA2, /* WPA2 */ + ENCRYP_PROTOCOL_WAPI, /* WAPI: Not support in this version */ + ENCRYP_PROTOCOL_MAX +}; + + +#ifndef Ndis802_11AuthModeWPA2 +#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) +#endif + +#ifndef Ndis802_11AuthModeWPA2PSK +#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) +#endif + +union pn48 { + u64 val; + +#ifdef __LITTLE_ENDIAN + struct { + u8 TSC0; + u8 TSC1; + u8 TSC2; + u8 TSC3; + u8 TSC4; + u8 TSC5; + u8 TSC6; + u8 TSC7; + } _byte_; + +#elif defined(__BIG_ENDIAN) + + struct { + u8 TSC7; + u8 TSC6; + u8 TSC5; + u8 TSC4; + u8 TSC3; + u8 TSC2; + u8 TSC1; + u8 TSC0; + } _byte_; +#endif +}; + +union Keytype { + u8 skey[16]; + u32 lkey[4]; +}; + +struct rt_pmkid_list { + u8 bUsed; + u8 Bssid[6]; + u8 PMKID[16]; + u8 SsidBuf[33]; + u8 *ssid_octet; + u16 ssid_length; +}; + +struct security_priv { + u32 dot11AuthAlgrthm; /* 802.11 auth, could be open, + * shared, 8021x and authswitch + */ + u32 dot11PrivacyAlgrthm; /* This specify the privacy for + * shared auth. algorithm. + */ + /* WEP */ + u32 dot11PrivacyKeyIndex; /* this is only valid for legendary + * wep, 0~3 for key id.(tx key index) + */ + union Keytype dot11DefKey[4]; /* this is only valid for def. key */ + u32 dot11DefKeylen[4]; + u32 dot118021XGrpPrivacy; /* This specify the privacy algthm. + * used for Grp key + */ + u32 dot118021XGrpKeyid; /* key id used for Grp Key + * ( tx key index) + */ + union Keytype dot118021XGrpKey[4]; /* 802.1x Group Key, + * for inx0 and inx1 + */ + union Keytype dot118021XGrptxmickey[4]; + union Keytype dot118021XGrprxmickey[4]; + union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit.*/ + union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv.*/ +#ifdef CPTCFG_88EU_AP_MODE + /* extend security capabilities for AP_MODE */ + unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */ + unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */ + unsigned int wpa_group_cipher; + unsigned int wpa2_group_cipher; + unsigned int wpa_pairwise_cipher; + unsigned int wpa2_pairwise_cipher; +#endif + u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */ + int wps_ie_len; + u8 binstallGrpkey; + u8 busetkipkey; + u8 bcheck_grpkey; + u8 bgrpkey_handshake; + s32 hw_decrypted;/* if the rx packets is hw_decrypted==false,i + * it means the hw has not been ready. + */ + + /* keeps the auth_type & enc_status from upper layer + * ioctl(wpa_supplicant or wzc) + */ + u32 ndisauthtype; /* NDIS_802_11_AUTHENTICATION_MODE */ + u32 ndisencryptstatus; /* NDIS_802_11_ENCRYPTION_STATUS */ + struct wlan_bssid_ex sec_bss; /* for joinbss (h2c buffer) usage */ + struct ndis_802_11_wep ndiswep; + u8 assoc_info[600]; + u8 szofcapability[256]; /* for wpa2 usage */ + u8 oidassociation[512]; /* for wpa/wpa2 usage */ + u8 authenticator_ie[256]; /* store ap security information element */ + u8 supplicant_ie[256]; /* store sta security information element */ + + /* for tkip countermeasure */ + u32 last_mic_err_time; + u8 btkip_countermeasure; + u8 btkip_wait_report; + u32 btkip_countermeasure_time; + + /* */ + /* For WPA2 Pre-Authentication. */ + /* */ + struct rt_pmkid_list PMKIDList[NUM_PMKID_CACHE]; + u8 PMKIDIndex; + u8 bWepDefaultKeyIdxSet; +}; + +#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst) \ +do { \ + switch (psecuritypriv->dot11AuthAlgrthm) { \ + case dot11AuthAlgrthm_Open: \ + case dot11AuthAlgrthm_Shared: \ + case dot11AuthAlgrthm_Auto: \ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm; \ + break; \ + case dot11AuthAlgrthm_8021X: \ + if (bmcst) \ + encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\ + else \ + encry_algo = (u8)psta->dot118021XPrivacy; \ + break; \ + case dot11AuthAlgrthm_WAPI: \ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm; \ + break; \ + } \ +} while (0) + +#define SET_ICE_IV_LEN(iv_len, icv_len, encrypt) \ +do { \ + switch (encrypt) { \ + case _WEP40_: \ + case _WEP104_: \ + iv_len = 4; \ + icv_len = 4; \ + break; \ + case _TKIP_: \ + iv_len = 8; \ + icv_len = 4; \ + break; \ + case _AES_: \ + iv_len = 8; \ + icv_len = 8; \ + break; \ + case _SMS4_: \ + iv_len = 18; \ + icv_len = 16; \ + break; \ + default: \ + iv_len = 0; \ + icv_len = 0; \ + break; \ + } \ +} while (0) + + +#define GET_TKIP_PN(iv, dot11txpn) \ +do { \ + dot11txpn._byte_.TSC0 = iv[2]; \ + dot11txpn._byte_.TSC1 = iv[0]; \ + dot11txpn._byte_.TSC2 = iv[4]; \ + dot11txpn._byte_.TSC3 = iv[5]; \ + dot11txpn._byte_.TSC4 = iv[6]; \ + dot11txpn._byte_.TSC5 = iv[7]; \ +} while (0) + + +#define ROL32(A, n) (((A) << (n)) | (((A)>>(32-(n))) & ((1UL << (n)) - 1))) +#define ROR32(A, n) ROL32((A), 32-(n)) + +struct mic_data { + u32 K0, K1; /* Key */ + u32 L, R; /* Current state */ + u32 M; /* Message accumulator (single word) */ + u32 nBytesInM; /* # bytes in M */ +}; + +extern const u32 Te0[256]; +extern const u32 Td0[256]; +extern const u32 Td1[256]; +extern const u32 Td2[256]; +extern const u32 Td3[256]; +extern const u32 Td4[256]; +extern const u32 rcon[10]; +extern const u8 Td4s[256]; +extern const u8 rcons[10]; + +#define RCON(i) (rcons[(i)] << 24) + +static inline u32 rotr(u32 val, int bits) +{ + return (val >> bits) | (val << (32 - bits)); +} + +#define TE0(i) Te0[((i) >> 24) & 0xff] +#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) +#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) +#define TE3(i) rotr(Te0[(i) & 0xff], 24) + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. + */ + +/* the K array */ +static const unsigned long K[64] = { + 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, + 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, + 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, + 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, + 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, + 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, + 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, + 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, + 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, + 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, + 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, + 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, + 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL +}; + +/* Various logical functions */ +#define RORc(x, y) \ + (((((unsigned long)(x) & 0xFFFFFFFFUL) >> (unsigned long)((y)&31)) | \ + ((unsigned long)(x) << (unsigned long)(32-((y)&31)))) & 0xFFFFFFFFUL) +#define Ch(x, y, z) (z ^ (x & (y ^ z))) +#define Maj(x, y, z) (((x | y) & z) | (x & y)) +#define S(x, n) RORc((x), (n)) +#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) +#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) +#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) +#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) +#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) + +void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key); +void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b); +void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes); +void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst); +void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, + u8 *Miccode, u8 priority); +u32 rtw_aes_encrypt(struct adapter *padapter, u8 *pxmitframe); +u32 rtw_tkip_encrypt(struct adapter *padapter, u8 *pxmitframe); +void rtw_wep_encrypt(struct adapter *padapter, u8 *pxmitframe); +u32 rtw_aes_decrypt(struct adapter *padapter, u8 *precvframe); +u32 rtw_tkip_decrypt(struct adapter *padapter, u8 *precvframe); +int rtw_wep_decrypt(struct adapter *padapter, u8 *precvframe); + +#endif /* __RTL871X_SECURITY_H_ */ diff --git a/drivers/staging/rtl8188eu/include/rtw_sreset.h b/drivers/staging/rtl8188eu/include/rtw_sreset.h new file mode 100644 index 0000000..3ee6a4a --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_sreset.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _RTW_SRESET_C_ +#define _RTW_SRESET_C_ + +#include <osdep_service.h> +#include <drv_types.h> + +struct sreset_priv { + u8 Wifi_Error_Status; +}; + +#include <rtl8188e_hal.h> + +#define WIFI_STATUS_SUCCESS 0 +#define USB_VEN_REQ_CMD_FAIL BIT(0) +#define USB_READ_PORT_FAIL BIT(1) +#define USB_WRITE_PORT_FAIL BIT(2) +#define WIFI_MAC_TXDMA_ERROR BIT(3) +#define WIFI_TX_HANG BIT(4) +#define WIFI_RX_HANG BIT(5) +#define WIFI_IF_NOT_EXIST BIT(6) + +void sreset_set_wifi_error_status(struct adapter *padapter, u32 status); + +#endif diff --git a/drivers/staging/rtl8188eu/include/rtw_xmit.h b/drivers/staging/rtl8188eu/include/rtw_xmit.h new file mode 100644 index 0000000..26a0824 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/rtw_xmit.h @@ -0,0 +1,358 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _RTW_XMIT_H_ +#define _RTW_XMIT_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +#define MAX_XMITBUF_SZ (20480) /* 20k */ +#define NR_XMITBUFF (4) + +#define XMITBUF_ALIGN_SZ 4 + +/* xmit extension buff defination */ +#define MAX_XMIT_EXTBUF_SZ (1536) +#define NR_XMIT_EXTBUFF (32) + +#define MAX_NUMBLKS (1) + +#define XMIT_VO_QUEUE (0) +#define XMIT_VI_QUEUE (1) +#define XMIT_BE_QUEUE (2) +#define XMIT_BK_QUEUE (3) + +#define VO_QUEUE_INX 0 +#define VI_QUEUE_INX 1 +#define BE_QUEUE_INX 2 +#define BK_QUEUE_INX 3 +#define BCN_QUEUE_INX 4 +#define MGT_QUEUE_INX 5 +#define HIGH_QUEUE_INX 6 +#define TXCMD_QUEUE_INX 7 + +#define HW_QUEUE_ENTRY 8 + +#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ +do {\ + pattrib_iv[0] = dot11txpn._byte_.TSC0;\ + pattrib_iv[1] = dot11txpn._byte_.TSC1;\ + pattrib_iv[2] = dot11txpn._byte_.TSC2;\ + pattrib_iv[3] = ((keyidx & 0x3)<<6);\ + dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val+1);\ +} while (0) + + +#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ +do {\ + pattrib_iv[0] = dot11txpn._byte_.TSC1;\ + pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ + pattrib_iv[2] = dot11txpn._byte_.TSC0;\ + pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ + pattrib_iv[4] = dot11txpn._byte_.TSC2;\ + pattrib_iv[5] = dot11txpn._byte_.TSC3;\ + pattrib_iv[6] = dot11txpn._byte_.TSC4;\ + pattrib_iv[7] = dot11txpn._byte_.TSC5;\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ +} while (0) + +#define AES_IV(pattrib_iv, dot11txpn, keyidx)\ +do { \ + pattrib_iv[0] = dot11txpn._byte_.TSC0; \ + pattrib_iv[1] = dot11txpn._byte_.TSC1; \ + pattrib_iv[2] = 0; \ + pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6); \ + pattrib_iv[4] = dot11txpn._byte_.TSC2; \ + pattrib_iv[5] = dot11txpn._byte_.TSC3; \ + pattrib_iv[6] = dot11txpn._byte_.TSC4; \ + pattrib_iv[7] = dot11txpn._byte_.TSC5; \ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ +} while (0) + +#define HWXMIT_ENTRY 4 + +#define TXDESC_SIZE 32 + +#define PACKET_OFFSET_SZ (8) +#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) + +struct tx_desc { + /* DWORD 0 */ + __le32 txdw0; + __le32 txdw1; + __le32 txdw2; + __le32 txdw3; + __le32 txdw4; + __le32 txdw5; + __le32 txdw6; + __le32 txdw7; +}; + +struct hw_xmit { + struct __queue *sta_queue; + int accnt; +}; + +/* reduce size */ +struct pkt_attrib { + u8 type; + u8 subtype; + u8 bswenc; + u8 dhcp_pkt; + u16 ether_type; + u16 seqnum; + u16 hdrlen; /* the WLAN Header Len */ + u32 pktlen; /* the original 802.3 pkt raw_data len (not include + * ether_hdr data) + */ + u32 last_txcmdsz; + u8 nr_frags; + u8 encrypt; /* when 0 indicate no encrypt. when non-zero, + * indicate the encrypt algorith + */ + u8 iv_len; + u8 icv_len; + u8 iv[18]; + u8 icv[16]; + u8 priority; + u8 ack_policy; + u8 mac_id; + u8 vcs_mode; /* virtual carrier sense method */ + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + u8 key_idx; + u8 qos_en; + u8 ht_en; + u8 raid;/* rate adpative id */ + u8 bwmode; + u8 ch_offset;/* PRIME_CHNL_OFFSET */ + u8 sgi;/* short GI */ + u8 ampdu_en;/* tx ampdu enable */ + u8 mdata;/* more data bit */ + u8 pctrl;/* per packet txdesc control enable */ + u8 triggered;/* for ap mode handling Power Saving sta */ + u8 qsel; + u8 eosp; + u8 rate; + u8 intel_proxim; + u8 retry_ctrl; + struct sta_info *psta; +}; + +#define WLANHDR_OFFSET 64 + +#define NULL_FRAMETAG (0x0) +#define DATA_FRAMETAG 0x01 +#define L2_FRAMETAG 0x02 +#define MGNT_FRAMETAG 0x03 +#define AMSDU_FRAMETAG 0x04 + +#define EII_FRAMETAG 0x05 +#define IEEE8023_FRAMETAG 0x06 + +#define MP_FRAMETAG 0x07 + +#define TXAGG_FRAMETAG 0x08 + +struct submit_ctx { + u32 submit_time; /* */ + u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ + int status; /* status for operation */ + struct completion done; +}; + +enum { + RTW_SCTX_SUBMITTED = -1, + RTW_SCTX_DONE_SUCCESS = 0, + RTW_SCTX_DONE_UNKNOWN, + RTW_SCTX_DONE_TIMEOUT, + RTW_SCTX_DONE_BUF_ALLOC, + RTW_SCTX_DONE_BUF_FREE, + RTW_SCTX_DONE_WRITE_PORT_ERR, + RTW_SCTX_DONE_TX_DESC_NA, + RTW_SCTX_DONE_TX_DENY, + RTW_SCTX_DONE_CCX_PKT_FAIL, + RTW_SCTX_DONE_DRV_STOP, + RTW_SCTX_DONE_DEV_REMOVE, +}; + +void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms); +int rtw_sctx_wait(struct submit_ctx *sctx); +void rtw_sctx_done_err(struct submit_ctx **sctx, int status); + +struct xmit_buf { + struct list_head list; + struct adapter *padapter; + u8 *pallocated_buf; + u8 *pbuf; + void *priv_data; + u16 ext_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf. */ + u16 flags; + u32 alloc_sz; + u32 len; + struct submit_ctx *sctx; + u32 ff_hwaddr; + struct urb *pxmit_urb[8]; + dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ + u8 bpending[8]; + int last[8]; +}; + +struct xmit_frame { + struct list_head list; + struct pkt_attrib attrib; + struct sk_buff *pkt; + int frame_tag; + struct adapter *padapter; + u8 *buf_addr; + struct xmit_buf *pxmitbuf; + + u8 agg_num; + s8 pkt_offset; + u8 ack_report; +}; + +struct tx_servq { + struct list_head tx_pending; + struct __queue sta_pending; + int qcnt; +}; + +struct sta_xmit_priv { + spinlock_t lock; + int option; + int apsd_setting; /* When bit mask is on, the associated edca + * queue supports APSD. + */ + struct tx_servq be_q; /* priority == 0,3 */ + struct tx_servq bk_q; /* priority == 1,2 */ + struct tx_servq vi_q; /* priority == 4,5 */ + struct tx_servq vo_q; /* priority == 6,7 */ + struct list_head legacy_dz; + struct list_head apsd; + u16 txseq_tid[16]; +}; + +struct hw_txqueue { + volatile int head; + volatile int tail; + volatile int free_sz; /* in units of 64 bytes */ + volatile int free_cmdsz; + volatile int txsz[8]; + uint ff_hwaddr; + uint cmd_hwaddr; + int ac_tag; +}; + +struct xmit_priv { + spinlock_t lock; + struct __queue be_pending; + struct __queue bk_pending; + struct __queue vi_pending; + struct __queue vo_pending; + struct __queue bm_pending; + u8 *pallocated_frame_buf; + u8 *pxmit_frame_buf; + uint free_xmitframe_cnt; + struct __queue free_xmit_queue; + uint frag_len; + struct adapter *adapter; + u8 vcs_setting; + u8 vcs; + u8 vcs_type; + u64 tx_bytes; + u64 tx_pkts; + u64 tx_drop; + u64 last_tx_bytes; + u64 last_tx_pkts; + struct hw_xmit *hwxmits; + u8 hwxmit_entry; + u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength + * from large to small. it's value is 0->vo, + * 1->vi, 2->be, 3->bk. + */ + u8 txirp_cnt;/* */ + struct tasklet_struct xmit_tasklet; + /* per AC pending irp */ + int beq_cnt; + int bkq_cnt; + int viq_cnt; + int voq_cnt; + struct __queue free_xmitbuf_queue; + struct __queue pending_xmitbuf_queue; + u8 *pallocated_xmitbuf; + u8 *pxmitbuf; + uint free_xmitbuf_cnt; + struct __queue free_xmit_extbuf_queue; + u8 *pallocated_xmit_extbuf; + u8 *pxmit_extbuf; + uint free_xmit_extbuf_cnt; + u16 nqos_ssn; + int ack_tx; + struct mutex ack_tx_mutex; + struct submit_ctx ack_tx_ops; +}; + +struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); +s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, + struct xmit_buf *pxmitbuf); +struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); +s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, + struct xmit_buf *pxmitbuf); +void rtw_count_tx_stats(struct adapter *padapter, + struct xmit_frame *pxmitframe, int sz); +void rtw_update_protection(struct adapter *padapter, u8 *ie, uint ie_len); +s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr, + struct pkt_attrib *pattrib); +s32 rtw_put_snap(u8 *data, u16 h_proto); + +struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); +s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, + struct xmit_frame *pxmitframe); +void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, + struct __queue *pframequeue); +struct tx_servq *rtw_get_sta_pending(struct adapter *padapter, + struct sta_info *psta, int up, u8 *ac); +s32 rtw_xmitframe_enqueue(struct adapter *padapter, + struct xmit_frame *pxmitframe); +struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, + struct hw_xmit *phwxmit_i, int entry); + +s32 rtw_xmit_classifier(struct adapter *padapter, + struct xmit_frame *pxmitframe); +s32 rtw_xmitframe_coalesce(struct adapter *padapter, struct sk_buff *pkt, + struct xmit_frame *pxmitframe); +s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag); +void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); +s32 rtw_txframes_pending(struct adapter *padapter); +s32 rtw_txframes_sta_ac_pending(struct adapter *padapter, + struct pkt_attrib *pattrib); +void rtw_init_hwxmits(struct hw_xmit *phwxmit, int entry); +s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter); +void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); +void rtw_alloc_hwxmits(struct adapter *padapter); +void rtw_free_hwxmits(struct adapter *padapter); +s32 rtw_xmit(struct adapter *padapter, struct sk_buff **pkt); + +#if defined(CPTCFG_88EU_AP_MODE) +int xmitframe_enqueue_for_sleeping_sta(struct adapter *padapter, struct xmit_frame *pxmitframe); +void stop_sta_xmit(struct adapter *padapter, struct sta_info *psta); +void wakeup_sta_to_xmit(struct adapter *padapter, struct sta_info *psta); +void xmit_delivery_enabled_frames(struct adapter *padapter, struct sta_info *psta); +#endif + +u8 qos_acm(u8 acm_mask, u8 priority); +u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); +int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); +void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); + +/* include after declaring struct xmit_buf, in order to avoid warning */ +#include <xmit_osdep.h> + +#endif /* _RTL871X_XMIT_H_ */ diff --git a/drivers/staging/rtl8188eu/include/sta_info.h b/drivers/staging/rtl8188eu/include/sta_info.h new file mode 100644 index 0000000..8da0d3e --- /dev/null +++ b/drivers/staging/rtl8188eu/include/sta_info.h @@ -0,0 +1,359 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __STA_INFO_H_ +#define __STA_INFO_H_ + +#include <osdep_service.h> +#include <drv_types.h> +#include <wifi.h> + +#define IBSS_START_MAC_ID 2 +#define NUM_STA 32 +#define NUM_ACL 16 + +/* if mode ==0, then the sta is allowed once the addr is hit. */ +/* if mode ==1, then the sta is rejected once the addr is non-hit. */ +struct rtw_wlan_acl_node { + struct list_head list; + u8 addr[ETH_ALEN]; + u8 valid; +}; + +/* mode=0, disable */ +/* mode=1, accept unless in deny list */ +/* mode=2, deny unless in accept list */ +struct wlan_acl_pool { + int mode; + int num; + struct rtw_wlan_acl_node aclnode[NUM_ACL]; + struct __queue acl_node_q; +}; + +struct rssi_sta { + s32 UndecoratedSmoothedPWDB; + s32 UndecoratedSmoothedCCK; + s32 UndecoratedSmoothedOFDM; + u64 PacketMap; + u8 ValidBit; +}; + +struct stainfo_stats { + u64 rx_mgnt_pkts; + u64 rx_beacon_pkts; + u64 rx_probereq_pkts; + u64 rx_probersp_pkts; + u64 rx_probersp_bm_pkts; + u64 rx_probersp_uo_pkts; + u64 rx_ctrl_pkts; + u64 rx_data_pkts; + + u64 last_rx_mgnt_pkts; + u64 last_rx_beacon_pkts; + u64 last_rx_probereq_pkts; + u64 last_rx_probersp_pkts; + u64 last_rx_probersp_bm_pkts; + u64 last_rx_probersp_uo_pkts; + u64 last_rx_ctrl_pkts; + u64 last_rx_data_pkts; + u64 rx_bytes; + u64 rx_drops; + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; +}; + +struct sta_info { + spinlock_t lock; + struct list_head list; /* free_sta_queue */ + struct list_head hash_list; /* sta_hash */ + + struct sta_xmit_priv sta_xmitpriv; + struct sta_recv_priv sta_recvpriv; + + struct __queue sleep_q; + unsigned int sleepq_len; + + uint state; + uint aid; + uint mac_id; + uint qos_option; + u8 hwaddr[ETH_ALEN]; + + uint ieee8021x_blocked; /* 0: allowed, 1:blocked */ + uint dot118021XPrivacy; /* aes, tkip... */ + union Keytype dot11tkiptxmickey; + union Keytype dot11tkiprxmickey; + union Keytype dot118021x_UncstKey; + union pn48 dot11txpn; /* PN48 used for Unicast xmit. */ + union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ + u8 bssrateset[16]; + u32 bssratelen; + s32 rssi; + s32 signal_quality; + + u8 cts2self; + u8 rtsen; + + u8 raid; + u8 init_rate; + u8 wireless_mode; /* NETWORK_TYPE */ + struct stainfo_stats sta_stats; + + /* for A-MPDU TX, ADDBA timeout check */ + struct timer_list addba_retry_timer; + + /* for A-MPDU Rx reordering buffer control */ + struct recv_reorder_ctrl recvreorder_ctrl[16]; + + /* for A-MPDU Tx */ + /* unsigned char ampdu_txen_bitmap; */ + u16 BA_starting_seqctrl[16]; + + struct ht_priv htpriv; + + /* Notes: */ + /* STA_Mode: */ + /* curr_network(mlme_priv/security_priv/qos/ht) + + * sta_info: (STA & AP) CAP/INFO + */ + /* scan_q: AP CAP/INFO */ + + /* AP_Mode: */ + /* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */ + /* sta_info: (AP & STA) CAP/INFO */ + + struct list_head asoc_list; +#ifdef CPTCFG_88EU_AP_MODE + struct list_head auth_list; + + unsigned int expire_to; + unsigned int auth_seq; + unsigned int authalg; + unsigned char chg_txt[128]; + + u16 capability; + int flags; + + int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */ + int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */ + int wpa_group_cipher; + int wpa2_group_cipher; + int wpa_pairwise_cipher; + int wpa2_pairwise_cipher; + + u8 bpairwise_key_installed; + + u8 wpa_ie[32]; + + u8 nonerp_set; + u8 no_short_slot_time_set; + u8 no_short_preamble_set; + u8 no_ht_gf_set; + u8 no_ht_set; + u8 ht_20mhz_set; + + unsigned int tx_ra_bitmap; + u8 qos_info; + + u8 max_sp_len; + u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */ + u8 uapsd_be; + u8 uapsd_vi; + u8 uapsd_vo; + + u8 has_legacy_ac; + unsigned int sleepq_ac_len; +#endif /* CPTCFG_88EU_AP_MODE */ + + u8 under_exist_checking; + u8 keep_alive_trycnt; + + /* for DM */ + struct rssi_sta rssi_stat; + + /* ================ODM Relative Info======================= */ + /* Please be careful, don't declare too much structure here. + * It will cost memory * STA support num. + */ + /* 2011/10/20 MH Add for ODM STA info. */ + /* Driver Write */ + u8 bValid; /* record the sta status link or not? */ + u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ + u8 rssi_level; /* for Refresh RA mask */ + /* ODM Write */ + /* 1 PHY_STATUS_INFO */ + u8 RSSI_Path[4]; /* */ + u8 RSSI_Ave; + u8 RXEVM[4]; + u8 RXSNR[4]; + + /* ================ODM Relative Info======================= */ + /* */ + + /* To store the sequence number of received management frame */ + u16 RxMgmtFrameSeqNum; +}; + +#define sta_rx_pkts(sta) \ + (sta->sta_stats.rx_mgnt_pkts \ + + sta->sta_stats.rx_ctrl_pkts \ + + sta->sta_stats.rx_data_pkts) + +#define sta_last_rx_pkts(sta) \ + (sta->sta_stats.last_rx_mgnt_pkts \ + + sta->sta_stats.last_rx_ctrl_pkts \ + + sta->sta_stats.last_rx_data_pkts) + +#define sta_rx_data_pkts(sta) \ + (sta->sta_stats.rx_data_pkts) + +#define sta_last_rx_data_pkts(sta) \ + (sta->sta_stats.last_rx_data_pkts) + +#define sta_rx_mgnt_pkts(sta) \ + (sta->sta_stats.rx_mgnt_pkts) + +#define sta_last_rx_mgnt_pkts(sta) \ + (sta->sta_stats.last_rx_mgnt_pkts) + +#define sta_rx_beacon_pkts(sta) \ + (sta->sta_stats.rx_beacon_pkts) + +#define sta_last_rx_beacon_pkts(sta) \ + (sta->sta_stats.last_rx_beacon_pkts) + +#define sta_rx_probereq_pkts(sta) \ + (sta->sta_stats.rx_probereq_pkts) + +#define sta_last_rx_probereq_pkts(sta) \ + (sta->sta_stats.last_rx_probereq_pkts) + +#define sta_rx_probersp_pkts(sta) \ + (sta->sta_stats.rx_probersp_pkts) + +#define sta_last_rx_probersp_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_pkts) + +#define sta_rx_probersp_bm_pkts(sta) \ + (sta->sta_stats.rx_probersp_bm_pkts) + +#define sta_last_rx_probersp_bm_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_bm_pkts) + +#define sta_rx_probersp_uo_pkts(sta) \ + (sta->sta_stats.rx_probersp_uo_pkts) + +#define sta_last_rx_probersp_uo_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_uo_pkts) + +#define sta_update_last_rx_pkts(sta) \ +do { \ + sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ + sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \ + sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \ + sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \ + sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \ + sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \ + sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ + sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ +} while (0) + +#define STA_RX_PKTS_ARG(sta) \ + sta->sta_stats.rx_mgnt_pkts \ + , sta->sta_stats.rx_ctrl_pkts \ + , sta->sta_stats.rx_data_pkts + +#define STA_LAST_RX_PKTS_ARG(sta) \ + sta->sta_stats.last_rx_mgnt_pkts \ + , sta->sta_stats.last_rx_ctrl_pkts \ + , sta->sta_stats.last_rx_data_pkts + +#define STA_RX_PKTS_DIFF_ARG(sta) \ + sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \ + , sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \ + , sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts + +#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" + +struct sta_priv { + u8 *pallocated_stainfo_buf; + u8 *pstainfo_buf; + struct __queue free_sta_queue; + + spinlock_t sta_hash_lock; + struct list_head sta_hash[NUM_STA]; + int asoc_sta_count; + struct __queue sleep_q; + struct __queue wakeup_q; + + struct adapter *padapter; + + spinlock_t asoc_list_lock; + struct list_head asoc_list; + +#ifdef CPTCFG_88EU_AP_MODE + struct list_head auth_list; + spinlock_t auth_list_lock; + u8 asoc_list_cnt; + u8 auth_list_cnt; + + unsigned int auth_to; /* sec, time to expire in authenticating. */ + unsigned int assoc_to; /* sec, time to expire before associating. */ + unsigned int expire_to; /* sec , time to expire after associated. */ + + /* pointers to STA info; based on allocated AID or NULL if AID free + * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 + * and so on + */ + struct sta_info *sta_aid[NUM_STA]; + + u16 sta_dz_bitmap;/* only support 15 stations, station aid bitmap + * for sleeping sta. + */ + u16 tim_bitmap; /* only support 15 stations, aid=0~15 mapping + * bit0~bit15 + */ + + u16 max_num_sta; + + struct wlan_acl_pool acl_list; +#endif + +}; + +static inline u32 wifi_mac_hash(u8 *mac) +{ + u32 x; + + x = mac[0]; + x = (x << 2) ^ mac[1]; + x = (x << 2) ^ mac[2]; + x = (x << 2) ^ mac[3]; + x = (x << 2) ^ mac[4]; + x = (x << 2) ^ mac[5]; + + x ^= x >> 8; + x = x & (NUM_STA - 1); + return x; +} + +u32 _rtw_init_sta_priv(struct sta_priv *pstapriv); +u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); + +#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0) +int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta); +struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int off); + +struct sta_info *rtw_alloc_stainfo(struct sta_priv *stapriv, u8 *hwaddr); +u32 rtw_free_stainfo(struct adapter *adapt, struct sta_info *psta); +void rtw_free_all_stainfo(struct adapter *adapt); +struct sta_info *rtw_get_stainfo(struct sta_priv *stapriv, u8 *hwaddr); +u32 rtw_init_bcmc_stainfo(struct adapter *adapt); +struct sta_info *rtw_get_bcmc_stainfo(struct adapter *padapter); +u8 rtw_access_ctrl(struct adapter *padapter, u8 *mac_addr); + +#endif /* _STA_INFO_H_ */ diff --git a/drivers/staging/rtl8188eu/include/usb_ops_linux.h b/drivers/staging/rtl8188eu/include/usb_ops_linux.h new file mode 100644 index 0000000..70d7297 --- /dev/null +++ b/drivers/staging/rtl8188eu/include/usb_ops_linux.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __USB_OPS_LINUX_H__ +#define __USB_OPS_LINUX_H__ + +#define VENDOR_CMD_MAX_DATA_LEN 254 + +#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10/* ms */ +#define RTW_USB_CONTROL_MSG_TIMEOUT 500/* ms */ + +#define MAX_USBCTRL_VENDORREQ_TIMES 10 + +#define RTW_USB_BULKOUT_TIME 5000/* ms */ + +#define REALTEK_USB_VENQT_READ 0xC0 +#define REALTEK_USB_VENQT_WRITE 0x40 + +#define ALIGNMENT_UNIT 16 +#define MAX_VENDOR_REQ_CMD_SIZE 254 /* 8188cu SIE Support */ +#define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT) + +#define USB_HIGH_SPEED_BULK_SIZE 512 +#define USB_FULL_SPEED_BULK_SIZE 64 + +#define _usbctrl_vendorreq_async_callback(urb, regs) \ + _usbctrl_vendorreq_async_callback(urb) +#define usb_bulkout_zero_complete(purb, regs) \ + usb_bulkout_zero_complete(purb) +#define usb_write_mem_complete(purb, regs) \ + usb_write_mem_complete(purb) +#define usb_write_port_complete(purb, regs) \ + usb_write_port_complete(purb) +#define usb_read_port_complete(purb, regs) \ + usb_read_port_complete(purb) +#define usb_read_interrupt_complete(purb, regs) \ + usb_read_interrupt_complete(purb) + +unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr); + +u8 usb_read8(struct adapter *adapter, u32 addr); +u16 usb_read16(struct adapter *adapter, u32 addr); +u32 usb_read32(struct adapter *adapter, u32 addr); + +u32 usb_read_port(struct adapter *adapter, u32 addr, struct recv_buf *precvbuf); +void usb_read_port_cancel(struct adapter *adapter); + +int usb_write8(struct adapter *adapter, u32 addr, u8 val); +int usb_write16(struct adapter *adapter, u32 addr, u16 val); +int usb_write32(struct adapter *adapter, u32 addr, u32 val); + +u32 usb_write_port(struct adapter *adapter, u32 addr, u32 cnt, struct xmit_buf *pmem); +void usb_write_port_cancel(struct adapter *adapter); + +#endif diff --git a/drivers/staging/rtl8188eu/include/wifi.h b/drivers/staging/rtl8188eu/include/wifi.h new file mode 100644 index 0000000..259bf2c --- /dev/null +++ b/drivers/staging/rtl8188eu/include/wifi.h @@ -0,0 +1,839 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef _WIFI_H_ +#define _WIFI_H_ + +#define WLAN_IEEE_OUI_LEN 3 +#define WLAN_CRC_LEN 4 +#define WLAN_BSSID_LEN 6 +#define WLAN_BSS_TS_LEN 8 +#define WLAN_HDR_A3_LEN 24 +#define WLAN_HDR_A4_LEN 30 +#define WLAN_HDR_A3_QOS_LEN 26 +#define WLAN_HDR_A4_QOS_LEN 32 +#define WLAN_DATA_MAXLEN 2312 + +#define WLAN_A3_PN_OFFSET 24 +#define WLAN_A4_PN_OFFSET 30 + +#define WLAN_MIN_ETHFRM_LEN 60 +#define WLAN_MAX_ETHFRM_LEN 1514 + +#define P80211CAPTURE_VERSION 0x80211001 + +/* This value is tested by WiFi 11n Test Plan 5.2.3. */ +/* This test verifies the WLAN NIC can update the NAV through sending + * the CTS with large duration. + */ +#define WiFiNavUpperUs 30000 /* 30 ms */ + +enum WIFI_FRAME_TYPE { + WIFI_MGT_TYPE = (0), + WIFI_CTRL_TYPE = (BIT(2)), + WIFI_DATA_TYPE = (BIT(3)), + WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /* QoS Data */ +}; + +enum WIFI_FRAME_SUBTYPE { + /* below is for mgt frame */ + WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE), + WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), + WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), + WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), + WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), + WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), + WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), + WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), + WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), + + /* below is for control frame */ + WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), + WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | + WIFI_CTRL_TYPE), + + /* below is for data frame */ + WIFI_DATA = (0 | WIFI_DATA_TYPE), + WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), + WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), + WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), + WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), + WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), +}; + +enum WIFI_REASON_CODE { + _RSON_RESERVED_ = 0, + _RSON_UNSPECIFIED_ = 1, + _RSON_AUTH_NO_LONGER_VALID_ = 2, + _RSON_DEAUTH_STA_LEAVING_ = 3, + _RSON_INACTIVITY_ = 4, + _RSON_UNABLE_HANDLE_ = 5, + _RSON_CLS2_ = 6, + _RSON_CLS3_ = 7, + _RSON_DISAOC_STA_LEAVING_ = 8, + _RSON_ASOC_NOT_AUTH_ = 9, + + /* WPA reason */ + _RSON_INVALID_IE_ = 13, + _RSON_MIC_FAILURE_ = 14, + _RSON_4WAY_HNDSHK_TIMEOUT_ = 15, + _RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16, + _RSON_DIFF_IE_ = 17, + _RSON_MLTCST_CIPHER_NOT_VALID_ = 18, + _RSON_UNICST_CIPHER_NOT_VALID_ = 19, + _RSON_AKMP_NOT_VALID_ = 20, + _RSON_UNSUPPORT_RSNE_VER_ = 21, + _RSON_INVALID_RSNE_CAP_ = 22, + _RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23, + + /* belowing are Realtek definition */ + _RSON_PMK_NOT_AVAILABLE_ = 24, + _RSON_TDLS_TEAR_TOOFAR_ = 25, + _RSON_TDLS_TEAR_UN_RSN_ = 26, +}; + +enum WIFI_STATUS_CODE { + _STATS_SUCCESSFUL_ = 0, + _STATS_FAILURE_ = 1, + _STATS_CAP_FAIL_ = 10, + _STATS_NO_ASOC_ = 11, + _STATS_OTHER_ = 12, + _STATS_NO_SUPP_ALG_ = 13, + _STATS_OUT_OF_AUTH_SEQ_ = 14, + _STATS_CHALLENGE_FAIL_ = 15, + _STATS_AUTH_TIMEOUT_ = 16, + _STATS_UNABLE_HANDLE_STA_ = 17, + _STATS_RATE_FAIL_ = 18, +}; + +enum WIFI_REG_DOMAIN { + DOMAIN_FCC = 1, + DOMAIN_IC = 2, + DOMAIN_ETSI = 3, + DOMAIN_SPA = 4, + DOMAIN_FRANCE = 5, + DOMAIN_MKK = 6, + DOMAIN_ISRAEL = 7, + DOMAIN_MKK1 = 8, + DOMAIN_MKK2 = 9, + DOMAIN_MKK3 = 10, + DOMAIN_MAX +}; + +#define _TO_DS_ BIT(8) +#define _FROM_DS_ BIT(9) +#define _MORE_FRAG_ BIT(10) +#define _RETRY_ BIT(11) +#define _PWRMGT_ BIT(12) +#define _MORE_DATA_ BIT(13) +#define _PRIVACY_ BIT(14) +#define _ORDER_ BIT(15) + +#define SetToDs(pbuf) \ + *(__le16 *)(pbuf) |= cpu_to_le16(_TO_DS_) + +#define GetToDs(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_TO_DS_)) != 0) + +#define ClearToDs(pbuf) \ + *(__le16 *)(pbuf) &= (~cpu_to_le16(_TO_DS_)) + +#define SetFrDs(pbuf) \ + *(__le16 *)(pbuf) |= cpu_to_le16(_FROM_DS_) + +#define GetFrDs(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_FROM_DS_)) != 0) + +#define ClearFrDs(pbuf) \ + *(__le16 *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)) + +#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) + + +#define SetMFrag(pbuf) \ + *(__le16 *)(pbuf) |= cpu_to_le16(_MORE_FRAG_) + +#define GetMFrag(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_MORE_FRAG_)) != 0) + +#define ClearMFrag(pbuf) \ + *(__le16 *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)) + +#define SetRetry(pbuf) \ + *(__le16 *)(pbuf) |= cpu_to_le16(_RETRY_) + +#define GetRetry(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_RETRY_)) != 0) + +#define ClearRetry(pbuf) \ + *(__le16 *)(pbuf) &= (~cpu_to_le16(_RETRY_)) + +#define SetPwrMgt(pbuf) \ + *(__le16 *)(pbuf) |= cpu_to_le16(_PWRMGT_) + +#define GetPwrMgt(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_PWRMGT_)) != 0) + +#define ClearPwrMgt(pbuf) \ + *(__le16 *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)) + +#define SetMData(pbuf) \ + *(__le16 *)(pbuf) |= cpu_to_le16(_MORE_DATA_) + +#define GetMData(pbuf) (((*(__le16 *)(pbuf)) & cpu_to_le16(_MORE_DATA_)) != 0) + +#define ClearMData(pbuf) \ + *(__le16 *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)) + +#define SetPrivacy(pbuf) \ + *(__le16 *)(pbuf) |= cpu_to_le16(_PRIVACY_) + +#define GetPrivacy(pbuf) \ + (((*(__le16 *)(pbuf)) & cpu_to_le16(_PRIVACY_)) != 0) + +#define GetOrder(pbuf) \ + (((*(__le16 *)(pbuf)) & cpu_to_le16(_ORDER_)) != 0) + +#define GetFrameType(pbuf) \ + (le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(3) | BIT(2))) + +#define GetFrameSubType(pbuf) (le16_to_cpu(*(__le16 *)(pbuf)) & (BIT(7) |\ + BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) + +#define SetFrameSubType(pbuf, type) \ + do { \ + *(__le16 *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | \ + BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ + *(__le16 *)(pbuf) |= cpu_to_le16(type); \ + } while (0) + +#define GetSequence(pbuf) \ + (le16_to_cpu(*(__le16 *)((size_t)(pbuf) + 22)) >> 4) + +#define GetFragNum(pbuf) \ + (le16_to_cpu(*(__le16 *)((size_t)(pbuf) + 22)) & 0x0f) + +#define SetSeqNum(pbuf, num) \ + do { \ + *(__le16 *)((size_t)(pbuf) + 22) = \ + ((*(__le16 *)((size_t)(pbuf) + 22)) & cpu_to_le16((unsigned short)0x000f)) | \ + cpu_to_le16((unsigned short)(0xfff0 & (num << 4))); \ + } while (0) + +#define SetDuration(pbuf, dur) \ + *(__le16 *)((size_t)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)) + + +#define SetPriority(pbuf, tid) \ + *(__le16 *)(pbuf) |= cpu_to_le16(tid & 0xf) + +#define GetPriority(pbuf) ((le16_to_cpu(*(__le16 *)(pbuf))) & 0xf) + +#define SetEOSP(pbuf, eosp) \ + *(__le16 *)(pbuf) |= cpu_to_le16((eosp & 1) << 4) + +#define SetAckpolicy(pbuf, ack) \ + *(__le16 *)(pbuf) |= cpu_to_le16((ack & 3) << 5) + +#define GetAckpolicy(pbuf) (((le16_to_cpu(*(__le16 *)pbuf)) >> 5) & 0x3) + +#define GetAMsdu(pbuf) (((le16_to_cpu(*(__le16 *)pbuf)) >> 7) & 0x1) + +#define GetAid(pbuf) (le16_to_cpu(*(__le16 *)((size_t)(pbuf) + 2)) & 0x3fff) + +#define GetAddr1Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 4)) + +#define GetAddr2Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 10)) + +#define GetAddr3Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 16)) + +#define GetAddr4Ptr(pbuf) ((unsigned char *)((size_t)(pbuf) + 24)) + +static inline int IS_MCAST(unsigned char *da) +{ + if ((*da) & 0x01) + return true; + else + return false; +} + +static inline unsigned char *get_da(unsigned char *pframe) +{ + unsigned char *da; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: /* ToDs=0, FromDs=0 */ + da = GetAddr1Ptr(pframe); + break; + case 0x01: /* ToDs=0, FromDs=1 */ + da = GetAddr1Ptr(pframe); + break; + case 0x02: /* ToDs=1, FromDs=0 */ + da = GetAddr3Ptr(pframe); + break; + default: /* ToDs=1, FromDs=1 */ + da = GetAddr3Ptr(pframe); + break; + } + return da; +} + +static inline unsigned char *get_sa(unsigned char *pframe) +{ + unsigned char *sa; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: /* ToDs=0, FromDs=0 */ + sa = GetAddr2Ptr(pframe); + break; + case 0x01: /* ToDs=0, FromDs=1 */ + sa = GetAddr3Ptr(pframe); + break; + case 0x02: /* ToDs=1, FromDs=0 */ + sa = GetAddr2Ptr(pframe); + break; + default: /* ToDs=1, FromDs=1 */ + sa = GetAddr4Ptr(pframe); + break; + } + return sa; +} + +static inline unsigned char *get_hdr_bssid(unsigned char *pframe) +{ + unsigned char *sa; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: /* ToDs=0, FromDs=0 */ + sa = GetAddr3Ptr(pframe); + break; + case 0x01: /* ToDs=0, FromDs=1 */ + sa = GetAddr2Ptr(pframe); + break; + case 0x02: /* ToDs=1, FromDs=0 */ + sa = GetAddr1Ptr(pframe); + break; + case 0x03: /* ToDs=1, FromDs=1 */ + sa = GetAddr1Ptr(pframe); + break; + default: + sa = NULL; /* */ + break; + } + return sa; +} + +static inline int IsFrameTypeCtrl(unsigned char *pframe) +{ + if (WIFI_CTRL_TYPE == GetFrameType(pframe)) + return true; + else + return false; +} +/*----------------------------------------------------------------------------- + Below is for the security related definition +------------------------------------------------------------------------------*/ +#define _RESERVED_FRAME_TYPE_ 0 +#define _SKB_FRAME_TYPE_ 2 +#define _PRE_ALLOCMEM_ 1 +#define _PRE_ALLOCHDR_ 3 +#define _PRE_ALLOCLLCHDR_ 4 +#define _PRE_ALLOCICVHDR_ 5 +#define _PRE_ALLOCMICHDR_ 6 + +#define _SIFSTIME_ \ + ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) ? 16 : 10) +#define _ACKCTSLNG_ 14 /* 14 bytes long, including crclng */ +#define _CRCLNG_ 4 + +#define _ASOCREQ_IE_OFFSET_ 4 /* excluding wlan_hdr */ +#define _ASOCRSP_IE_OFFSET_ 6 +#define _REASOCREQ_IE_OFFSET_ 10 +#define _REASOCRSP_IE_OFFSET_ 6 +#define _PROBEREQ_IE_OFFSET_ 0 +#define _PROBERSP_IE_OFFSET_ 12 +#define _AUTH_IE_OFFSET_ 6 +#define _DEAUTH_IE_OFFSET_ 0 +#define _BEACON_IE_OFFSET_ 12 +#define _PUBLIC_ACTION_IE_OFFSET_ 8 + +#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ + +#define _SSID_IE_ 0 +#define _SUPPORTEDRATES_IE_ 1 +#define _DSSET_IE_ 3 +#define _TIM_IE_ 5 +#define _IBSS_PARA_IE_ 6 +#define _COUNTRY_IE_ 7 +#define _CHLGETXT_IE_ 16 +#define _SUPPORTED_CH_IE_ 36 +#define _CH_SWTICH_ANNOUNCE_ 37 /* Secondary Channel Offset */ +#define _RSN_IE_2_ 48 +#define _SSN_IE_1_ 221 +#define _ERPINFO_IE_ 42 +#define _EXT_SUPPORTEDRATES_IE_ 50 + +#define _HT_CAPABILITY_IE_ 45 +#define _FTIE_ 55 +#define _TIMEOUT_ITVL_IE_ 56 +#define _SRC_IE_ 59 +#define _HT_EXTRA_INFO_IE_ 61 +#define _HT_ADD_INFO_IE_ 61 /* _HT_EXTRA_INFO_IE_ */ +#define _WAPI_IE_ 68 + + +#define EID_BSSCoexistence 72 /* 20/40 BSS Coexistence */ +#define EID_BSSIntolerantChlReport 73 +#define _RIC_Descriptor_IE_ 75 + +#define _LINK_ID_IE_ 101 +#define _CH_SWITCH_TIMING_ 104 +#define _PTI_BUFFER_STATUS_ 106 +#define _EXT_CAP_IE_ 127 +#define _VENDOR_SPECIFIC_IE_ 221 + +#define _RESERVED47_ 47 + +/* --------------------------------------------------------------------------- + Below is the fixed elements... +-----------------------------------------------------------------------------*/ +#define _AUTH_ALGM_NUM_ 2 +#define _AUTH_SEQ_NUM_ 2 +#define _BEACON_ITERVAL_ 2 +#define _CAPABILITY_ 2 +#define _CURRENT_APADDR_ 6 +#define _LISTEN_INTERVAL_ 2 +#define _RSON_CODE_ 2 +#define _ASOC_ID_ 2 +#define _STATUS_CODE_ 2 +#define _TIMESTAMP_ 8 + +#define AUTH_ODD_TO 0 +#define AUTH_EVEN_TO 1 + +#define WLAN_ETHCONV_ENCAP 1 +#define WLAN_ETHCONV_RFC1042 2 +#define WLAN_ETHCONV_8021h 3 + +#define cap_ESS BIT(0) +#define cap_IBSS BIT(1) +#define cap_CFPollable BIT(2) +#define cap_CFRequest BIT(3) +#define cap_Privacy BIT(4) +#define cap_ShortPremble BIT(5) +#define cap_PBCC BIT(6) +#define cap_ChAgility BIT(7) +#define cap_SpecMgmt BIT(8) +#define cap_QoSi BIT(9) +#define cap_ShortSlot BIT(10) + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11i / 802.1x +------------------------------------------------------------------------------*/ +#define _IEEE8021X_MGT_ 1 /* WPA */ +#define _IEEE8021X_PSK_ 2 /* WPA with pre-shared key */ + +/* + * #define _NO_PRIVACY_ 0 + * #define _WEP_40_PRIVACY_ 1 + * #define _TKIP_PRIVACY_ 2 + * #define _WRAP_PRIVACY_ 3 + * #define _CCMP_PRIVACY_ 4 + * #define _WEP_104_PRIVACY_ 5 + * #define _WEP_WPA_MIXED_PRIVACY_ 6 WEP + WPA + */ + +/*----------------------------------------------------------------------------- + Below is the definition for WMM +------------------------------------------------------------------------------*/ +#define _WMM_IE_Length_ 7 /* for WMM STA */ +#define _WMM_Para_Element_Length_ 24 + + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11n +------------------------------------------------------------------------------*/ + +/* 802.11 BAR control masks */ +#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL 0x0000 +#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA 0x0004 + +/** + * struct rtw_ieee80211_ht_cap - HT additional information + * + * This structure refers to "HT information element" as + * described in 802.11n draft section 7.3.2.53 + */ +struct ieee80211_ht_addt_info { + unsigned char control_chan; + unsigned char ht_param; + unsigned short operation_mode; + unsigned short stbc_param; + unsigned char basic_set[16]; +} __packed; + +struct HT_info_element { + unsigned char primary_channel; + unsigned char infos[5]; + unsigned char MCS_rate[16]; +} __packed; + +struct AC_param { + unsigned char ACI_AIFSN; + unsigned char CW; + __le16 TXOP_limit; +} __packed; + +struct WMM_para_element { + unsigned char QoS_info; + unsigned char reserved; + struct AC_param ac_param[4]; +} __packed; + +struct ADDBA_request { + unsigned char dialog_token; + __le16 BA_para_set; + unsigned short BA_timeout_value; + unsigned short BA_starting_seqctrl; +} __packed; + +enum ht_cap_ampdu_factor { + MAX_AMPDU_FACTOR_8K = 0, + MAX_AMPDU_FACTOR_16K = 1, + MAX_AMPDU_FACTOR_32K = 2, + MAX_AMPDU_FACTOR_64K = 3, +}; + +/* 802.11n HT capabilities masks */ +#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002 +#define IEEE80211_HT_CAP_SM_PS 0x000C +#define IEEE80211_HT_CAP_GRN_FLD 0x0010 +#define IEEE80211_HT_CAP_SGI_20 0x0020 +#define IEEE80211_HT_CAP_SGI_40 0x0040 +#define IEEE80211_HT_CAP_TX_STBC 0x0080 +#define IEEE80211_HT_CAP_RX_STBC 0x0300 +#define IEEE80211_HT_CAP_DELAY_BA 0x0400 +#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 +#define IEEE80211_HT_CAP_DSSSCCK40 0x1000 +/* 802.11n HT capability AMPDU settings */ +#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 +#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C +/* 802.11n HT capability MSC set */ +#define IEEE80211_SUPP_MCS_SET_UEQM 4 +#define IEEE80211_HT_CAP_MAX_STREAMS 4 +#define IEEE80211_SUPP_MCS_SET_LEN 10 +/* maximum streams the spec allows */ +#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 +#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 +#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C +#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 +/* 802.11n HT IE masks */ +#define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03 +#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00 +#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01 +#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03 +#define IEEE80211_HT_IE_CHA_WIDTH 0x04 +#define IEEE80211_HT_IE_HT_PROTECTION 0x0003 +#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 +#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 + +/* block-ack parameters */ +#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 +#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C +#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0 +#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 +#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 + +/* + * A-PMDU buffer sizes + * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) + */ +#define IEEE80211_MIN_AMPDU_BUF 0x8 + + +#define OP_MODE_PURE 0 +#define OP_MODE_MAY_BE_LEGACY_STAS 1 +#define OP_MODE_20MHZ_HT_STA_ASSOCED 2 +#define OP_MODE_MIXED 3 + +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8)BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8)BIT(0)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8)BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8)BIT(2)) +#define HT_INFO_HT_PARAM_RIFS_MODE ((u8)BIT(3)) +#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8)BIT(4)) +#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8)BIT(5)) + +#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \ + ((u16)(0x0001 | 0x0002)) +#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0 +#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8)BIT(2)) +#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8)BIT(3)) +#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8)BIT(4)) + +#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16)BIT(6)) +#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16)BIT(7)) +#define HT_INFO_STBC_PARAM_SECONDARY_BC ((u16)BIT(8)) +#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16)BIT(9)) +#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16)BIT(10)) +#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16)BIT(11)) + +/* ===============WPS Section=============== */ +/* For WPSv1.0 */ +#define WPSOUI 0x0050f204 +/* WPS attribute ID */ +#define WPS_ATTR_VER1 0x104A +#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 +#define WPS_ATTR_RESP_TYPE 0x103B +#define WPS_ATTR_UUID_E 0x1047 +#define WPS_ATTR_MANUFACTURER 0x1021 +#define WPS_ATTR_MODEL_NAME 0x1023 +#define WPS_ATTR_MODEL_NUMBER 0x1024 +#define WPS_ATTR_SERIAL_NUMBER 0x1042 +#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 +#define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055 +#define WPS_ATTR_DEVICE_NAME 0x1011 +#define WPS_ATTR_CONF_METHOD 0x1008 +#define WPS_ATTR_RF_BANDS 0x103C +#define WPS_ATTR_DEVICE_PWID 0x1012 +#define WPS_ATTR_REQUEST_TYPE 0x103A +#define WPS_ATTR_ASSOCIATION_STATE 0x1002 +#define WPS_ATTR_CONFIG_ERROR 0x1009 +#define WPS_ATTR_VENDOR_EXT 0x1049 +#define WPS_ATTR_SELECTED_REGISTRAR 0x1041 + +/* Value of WPS Request Type Attribute */ +#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 +#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 +#define WPS_REQ_TYPE_REGISTRAR 0x02 +#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 + +/* Value of WPS Response Type Attribute */ +#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 +#define WPS_RESPONSE_TYPE_8021X 0x01 +#define WPS_RESPONSE_TYPE_REGISTRAR 0x02 +#define WPS_RESPONSE_TYPE_AP 0x03 + +/* Value of WPS WiFi Simple Configuration State Attribute */ +#define WPS_WSC_STATE_NOT_CONFIG 0x01 +#define WPS_WSC_STATE_CONFIG 0x02 + +/* Value of WPS Version Attribute */ +#define WPS_VERSION_1 0x10 + +/* Value of WPS Configuration Method Attribute */ +#define WPS_CONFIG_METHOD_FLASH 0x0001 +#define WPS_CONFIG_METHOD_ETHERNET 0x0002 +#define WPS_CONFIG_METHOD_LABEL 0x0004 +#define WPS_CONFIG_METHOD_DISPLAY 0x0008 +#define WPS_CONFIG_METHOD_E_NFC 0x0010 +#define WPS_CONFIG_METHOD_I_NFC 0x0020 +#define WPS_CONFIG_METHOD_NFC 0x0040 +#define WPS_CONFIG_METHOD_PBC 0x0080 +#define WPS_CONFIG_METHOD_KEYPAD 0x0100 +#define WPS_CONFIG_METHOD_VPBC 0x0280 +#define WPS_CONFIG_METHOD_PPBC 0x0480 +#define WPS_CONFIG_METHOD_VDISPLAY 0x2008 +#define WPS_CONFIG_METHOD_PDISPLAY 0x4008 + +/* Value of Category ID of WPS Primary Device Type Attribute */ +#define WPS_PDT_CID_DISPLAYS 0x0007 +#define WPS_PDT_CID_MULIT_MEDIA 0x0008 +#define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA + +/* Value of Sub Category ID of WPS Primary Device Type Attribute */ +#define WPS_PDT_SCID_MEDIA_SERVER 0x0005 +#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER + +/* Value of Device Password ID */ +#define WPS_DPID_P 0x0000 +#define WPS_DPID_USER_SPEC 0x0001 +#define WPS_DPID_MACHINE_SPEC 0x0002 +#define WPS_DPID_REKEY 0x0003 +#define WPS_DPID_PBC 0x0004 +#define WPS_DPID_REGISTRAR_SPEC 0x0005 + +/* Value of WPS RF Bands Attribute */ +#define WPS_RF_BANDS_2_4_GHZ 0x01 +#define WPS_RF_BANDS_5_GHZ 0x02 + +/* Value of WPS Association State Attribute */ +#define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00 +#define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01 +#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02 +#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 +#define WPS_ASSOC_STATE_IP_FAILURE 0x04 + +/* =====================P2P Section===================== */ +/* For P2P */ +#define P2POUI 0x506F9A09 + +/* P2P Attribute ID */ +#define P2P_ATTR_STATUS 0x00 +#define P2P_ATTR_MINOR_REASON_CODE 0x01 +#define P2P_ATTR_CAPABILITY 0x02 +#define P2P_ATTR_DEVICE_ID 0x03 +#define P2P_ATTR_GO_INTENT 0x04 +#define P2P_ATTR_CONF_TIMEOUT 0x05 +#define P2P_ATTR_LISTEN_CH 0x06 +#define P2P_ATTR_GROUP_BSSID 0x07 +#define P2P_ATTR_EX_LISTEN_TIMING 0x08 +#define P2P_ATTR_INTENTED_IF_ADDR 0x09 +#define P2P_ATTR_MANAGEABILITY 0x0A +#define P2P_ATTR_CH_LIST 0x0B +#define P2P_ATTR_NOA 0x0C +#define P2P_ATTR_DEVICE_INFO 0x0D +#define P2P_ATTR_GROUP_INFO 0x0E +#define P2P_ATTR_GROUP_ID 0x0F +#define P2P_ATTR_INTERFACE 0x10 +#define P2P_ATTR_OPERATING_CH 0x11 +#define P2P_ATTR_INVITATION_FLAGS 0x12 + +/* Value of Status Attribute */ +#define P2P_STATUS_SUCCESS 0x00 +#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 +#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 +#define P2P_STATUS_FAIL_INVALID_PARAM 0x04 +#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 +#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 +#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 +#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 +#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A +#define P2P_STATUS_FAIL_USER_REJECT 0x0B + +/* Value of Invitation Flags Attribute */ + +/* Value of Device Capability Bitmap */ +#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) +#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) +#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) +#define P2P_DEVCAP_INFRA_MANAGED BIT(3) +#define P2P_DEVCAP_DEVICE_LIMIT BIT(4) +#define P2P_DEVCAP_INVITATION_PROC BIT(5) + +/* Value of Group Capability Bitmap */ +#define P2P_GRPCAP_GO BIT(0) +#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) +#define P2P_GRPCAP_GROUP_LIMIT BIT(2) +#define P2P_GRPCAP_INTRABSS BIT(3) +#define P2P_GRPCAP_CROSS_CONN BIT(4) +#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) +#define P2P_GRPCAP_GROUP_FORMATION BIT(6) + +/* P2P Public Action Frame (Management Frame) */ +#define P2P_PUB_ACTION_ACTION 0x09 + +/* P2P Public Action Frame Type */ +#define P2P_GO_NEGO_REQ 0 +#define P2P_GO_NEGO_RESP 1 +#define P2P_GO_NEGO_CONF 2 +#define P2P_INVIT_REQ 3 +#define P2P_INVIT_RESP 4 +#define P2P_DEVDISC_REQ 5 +#define P2P_DEVDISC_RESP 6 +#define P2P_PROVISION_DISC_REQ 7 +#define P2P_PROVISION_DISC_RESP 8 + +/* P2P Action Frame Type */ +#define P2P_NOTICE_OF_ABSENCE 0 +#define P2P_PRESENCE_REQUEST 1 +#define P2P_PRESENCE_RESPONSE 2 +#define P2P_GO_DISC_REQUEST 3 + +#define P2P_PROVISIONING_SCAN_CNT 3 + +/* default value, used when: (1)p2p disabled or (2)p2p enabled + * but only do 1 scan phase + */ +#define P2P_FINDPHASE_EX_NONE 0 +/* used when p2p enabled and want to do 1 scan phase and + * P2P_FINDPHASE_EX_MAX-1 find phase + */ +#define P2P_FINDPHASE_EX_FULL 1 +#define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1) +#define P2P_FINDPHASE_EX_MAX 4 +#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX + +/* 5 seconds timeout for sending the provision discovery request */ +#define P2P_PROVISION_TIMEOUT 5000 +/* 3 seconds timeout for sending the prov disc request concurrent mode */ +#define P2P_CONCURRENT_PROVISION_TIME 3000 +/* 5 seconds timeout for receiving the group negotiation response */ +#define P2P_GO_NEGO_TIMEOUT 5000 +/* 3 seconds timeout for sending the negotiation request under concurrent mode */ +#define P2P_CONCURRENT_GO_NEGO_TIME 3000 +/* 100ms */ +#define P2P_TX_PRESCAN_TIMEOUT 100 +/* 5 seconds timeout for sending the invitation request */ +#define P2P_INVITE_TIMEOUT 5000 +/* 3 seconds timeout for sending the invitation request under concurrent mode */ +#define P2P_CONCURRENT_INVITE_TIME 3000 +/* 25 seconds timeout to reset the scan channel (based on channel plan) */ +#define P2P_RESET_SCAN_CH 25000 +#define P2P_MAX_INTENT 15 + +/* WPS Configuration Method */ +#define WPS_CM_NONE 0x0000 +#define WPS_CM_LABEL 0x0004 +#define WPS_CM_DISPLYA 0x0008 +#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 +#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 +#define WPS_CM_NFC_INTERFACE 0x0040 +#define WPS_CM_PUSH_BUTTON 0x0080 +#define WPS_CM_KEYPAD 0x0100 +#define WPS_CM_SW_PUHS_BUTTON 0x0280 +#define WPS_CM_HW_PUHS_BUTTON 0x0480 +#define WPS_CM_SW_DISPLAY_P 0x2008 +#define WPS_CM_LCD_DISPLAY_P 0x4008 + +#define P2P_PRIVATE_IOCTL_SET_LEN 64 + +enum P2P_PROTO_WK_ID { + P2P_FIND_PHASE_WK = 0, + P2P_RESTORE_STATE_WK = 1, + P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, + P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, + P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, + P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5, + P2P_RO_CH_WK = 6, +}; + +/* =====================WFD Section===================== */ +/* For Wi-Fi Display */ +#define WFD_ATTR_DEVICE_INFO 0x00 +#define WFD_ATTR_ASSOC_BSSID 0x01 +#define WFD_ATTR_COUPLED_SINK_INFO 0x06 +#define WFD_ATTR_LOCAL_IP_ADDR 0x08 +#define WFD_ATTR_SESSION_INFO 0x09 +#define WFD_ATTR_ALTER_MAC 0x0a + +/* For WFD Device Information Attribute */ +#define WFD_DEVINFO_SOURCE 0x0000 +#define WFD_DEVINFO_PSINK 0x0001 +#define WFD_DEVINFO_SSINK 0x0002 +#define WFD_DEVINFO_DUAL 0x0003 + +#define WFD_DEVINFO_SESSION_AVAIL 0x0010 +#define WFD_DEVINFO_WSD 0x0040 +#define WFD_DEVINFO_PC_TDLS 0x0080 +#define WFD_DEVINFO_HDCP_SUPPORT 0x0100 + +#define IP_MCAST_MAC(mac) \ + ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) +#define ICMPV6_MCAST_MAC(mac) \ + ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff)) + +#endif /* _WIFI_H_ */ diff --git a/drivers/staging/rtl8188eu/include/wlan_bssdef.h b/drivers/staging/rtl8188eu/include/wlan_bssdef.h new file mode 100644 index 0000000..5e13a6d --- /dev/null +++ b/drivers/staging/rtl8188eu/include/wlan_bssdef.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __WLAN_BSSDEF_H__ +#define __WLAN_BSSDEF_H__ + + +#define MAX_IE_SZ 768 + +#define NDIS_802_11_LENGTH_SSID 32 +#define NDIS_802_11_LENGTH_RATES 8 +#define NDIS_802_11_LENGTH_RATES_EX 16 + +#define NDIS_802_11_RSSI long /* in dBm */ + +struct ndis_802_11_ssid { + u32 SsidLength; + u8 Ssid[32]; +}; + +enum NDIS_802_11_NETWORK_TYPE { + Ndis802_11FH, + Ndis802_11DS, + Ndis802_11OFDM5, + Ndis802_11OFDM24, + Ndis802_11NetworkTypeMax /* dummy upper bound */ +}; + +struct ndis_802_11_config_fh { + u32 Length; /* Length of structure */ + u32 HopPattern; /* As defined by 802.11, MSB set */ + u32 HopSet; /* to one if non-802.11 */ + u32 DwellTime; /* units are Kusec */ +}; + +/* + * FW will only save the channel number in DSConfig. + * ODI Handler will convert the channel number to freq. number. + */ +struct ndis_802_11_config { + u32 Length; /* Length of structure */ + u32 BeaconPeriod; /* units are Kusec */ + u32 ATIMWindow; /* units are Kusec */ + u32 DSConfig; /* Frequency, units are kHz */ + struct ndis_802_11_config_fh FHConfig; +}; + +enum ndis_802_11_network_infra { + Ndis802_11IBSS, + Ndis802_11Infrastructure, + Ndis802_11AutoUnknown, + Ndis802_11InfrastructureMax, /* dummy upper bound */ + Ndis802_11APMode +}; + +struct ndis_802_11_fixed_ie { + u8 Timestamp[8]; + u16 BeaconInterval; + u16 Capabilities; +}; + + + +struct ndis_802_11_var_ie { + u8 ElementID; + u8 Length; + u8 data[1]; +}; + +/* + * Length is the 4 bytes multiples of the sume of + * [ETH_ALEN] + 2 + sizeof (struct ndis_802_11_ssid) + sizeof (u32) + * + sizeof (NDIS_802_11_RSSI) + sizeof (enum NDIS_802_11_NETWORK_TYPE) + * + sizeof (struct ndis_802_11_config) + * + NDIS_802_11_LENGTH_RATES_EX + ie_length + * + * Except the ie_length, all other fields are fixed length. + * Therefore, we can define a macro to represent the partial sum. + */ + +enum ndis_802_11_auth_mode { + Ndis802_11AuthModeOpen, + Ndis802_11AuthModeShared, + Ndis802_11AuthModeAutoSwitch, + Ndis802_11AuthModeWPA, + Ndis802_11AuthModeWPAPSK, + Ndis802_11AuthModeWPANone, + Ndis802_11AuthModeWAPI, + Ndis802_11AuthModeMax /* Not a real mode, upper bound */ +}; + +enum ndis_802_11_wep_status { + Ndis802_11WEPEnabled, + Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, + Ndis802_11WEPDisabled, + Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, + Ndis802_11WEPKeyAbsent, + Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, + Ndis802_11WEPNotSupported, + Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, + Ndis802_11Encryption2Enabled, + Ndis802_11Encryption2KeyAbsent, + Ndis802_11Encryption3Enabled, + Ndis802_11Encryption3KeyAbsent, + Ndis802_11_EncryptionWAPI +}; + +#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 +#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 +#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 + +#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 +#define NDIS_802_11_AI_RESFI_STATUSCODE 2 +#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 + +enum ndis_802_11_reload_def { + Ndis802_11ReloadWEPKeys +}; + +struct ndis_802_11_wep { + u32 Length; /* Length of this structure */ + u32 KeyIndex; /* 0 is the per-client key, + * 1-N are the global keys + */ + u32 KeyLength; /* length of key in bytes */ + u8 KeyMaterial[16];/* variable len depending on above field */ +}; + +enum ndis_802_11_status_type { + Ndis802_11StatusType_Authentication, + Ndis802_11StatusType_MediaStreamMode, + Ndis802_11StatusType_PMKID_CandidateList, + Ndis802_11StatusTypeMax /* not a real type, defined as + * an upper bound + */ +}; + +/* mask for authentication/integrity fields */ +#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f +#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 +#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 +#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 +#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E + +/* MIC check time, 60 seconds. */ +#define MIC_CHECK_TIME 60000000 + +#ifndef Ndis802_11APMode +#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) +#endif + +struct wlan_phy_info { + u8 SignalStrength;/* in percentage) */ + u8 SignalQuality;/* in percentage) */ + u8 Optimum_antenna; /* for Antenna diversity */ + u8 Reserved_0; +}; + +struct wlan_bcn_info { + /* these infor get from rtw_get_encrypt_info when + * * translate scan to UI + */ + u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */ + int group_cipher; /* WPA/WPA2 group cipher */ + int pairwise_cipher;/* WPA/WPA2/WEP pairwise cipher */ + int is_8021x; + + /* bwmode 20/40 and ch_offset UP/LOW */ + unsigned short ht_cap_info; + unsigned char ht_info_infos_0; +}; + +/* temporally add #pragma pack for structure alignment issue of + * struct wlan_bssid_ex and get_struct wlan_bssid_ex_sz() + */ +struct wlan_bssid_ex { + u32 Length; + unsigned char MacAddress[ETH_ALEN]; + u8 Reserved[2];/* 0]: IS beacon frame */ + struct ndis_802_11_ssid Ssid; + u32 Privacy; + NDIS_802_11_RSSI Rssi;/* in dBM,raw data ,get from PHY) */ + enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + struct ndis_802_11_config Configuration; + enum ndis_802_11_network_infra InfrastructureMode; + unsigned char SupportedRates[NDIS_802_11_LENGTH_RATES_EX]; + struct wlan_phy_info PhyInfo; + u32 ie_length; + u8 ies[MAX_IE_SZ]; /* timestamp, beacon interval, and + * capability information) + */ +} __packed; + +static inline uint get_wlan_bssid_ex_sz(struct wlan_bssid_ex *bss) +{ + return sizeof(struct wlan_bssid_ex) - MAX_IE_SZ + bss->ie_length; +} + +struct wlan_network { + struct list_head list; + int network_type; /* refer to ieee80211.h for WIRELESS_11A/B/G */ + int fixed; /* set fixed when not to be removed + * in site-surveying + */ + unsigned long last_scanned; /* timestamp for the network */ + int aid; /* will only be valid when a BSS is joinned. */ + int join_res; + struct wlan_bssid_ex network; /* must be the last item */ + struct wlan_bcn_info BcnInfo; +}; + +enum VRTL_CARRIER_SENSE { + DISABLE_VCS, + ENABLE_VCS, + AUTO_VCS +}; + +enum VCS_TYPE { + NONE_VCS, + RTS_CTS, + CTS_TO_SELF +}; + +#define PWR_CAM 0 +#define PWR_MINPS 1 +#define PWR_MAXPS 2 +#define PWR_UAPSD 3 +#define PWR_VOIP 4 + +enum UAPSD_MAX_SP { + NO_LIMIT, + TWO_MSDU, + FOUR_MSDU, + SIX_MSDU +}; + +#define NUM_PRE_AUTH_KEY 16 +#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY + +#endif /* ifndef WLAN_BSSDEF_H_ */ diff --git a/drivers/staging/rtl8188eu/include/xmit_osdep.h b/drivers/staging/rtl8188eu/include/xmit_osdep.h new file mode 100644 index 0000000..5283a6d --- /dev/null +++ b/drivers/staging/rtl8188eu/include/xmit_osdep.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + ******************************************************************************/ +#ifndef __XMIT_OSDEP_H_ +#define __XMIT_OSDEP_H_ + +#include <osdep_service.h> +#include <drv_types.h> + +#define NR_XMITFRAME 256 + +struct xmit_priv; +struct pkt_attrib; +struct sta_xmit_priv; +struct xmit_frame; +struct xmit_buf; + +int rtw_xmit_entry(struct sk_buff *pkt, struct net_device *pnetdev); + +void rtw_os_xmit_schedule(struct adapter *padapter); + +int rtw_os_xmit_resource_alloc(struct adapter *padapter, + struct xmit_buf *pxmitbuf, u32 alloc_sz); +void rtw_os_xmit_resource_free(struct xmit_buf *pxmitbuf); + +void rtw_os_pkt_complete(struct adapter *padapter, struct sk_buff *pkt); +void rtw_os_xmit_complete(struct adapter *padapter, + struct xmit_frame *pxframe); + +#endif /* __XMIT_OSDEP_H_ */ |